DE69633577D1 - Schwebegatterspeicheranordnung mit seitenpuffer mit niedrigem strom - Google Patents
Schwebegatterspeicheranordnung mit seitenpuffer mit niedrigem stromInfo
- Publication number
- DE69633577D1 DE69633577D1 DE69633577T DE69633577T DE69633577D1 DE 69633577 D1 DE69633577 D1 DE 69633577D1 DE 69633577 T DE69633577 T DE 69633577T DE 69633577 T DE69633577 T DE 69633577T DE 69633577 D1 DE69633577 D1 DE 69633577D1
- Authority
- DE
- Germany
- Prior art keywords
- floating gate
- low current
- current side
- gate memory
- side buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
- G11C11/5635—Erasing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5621—Multilevel programming verification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/562—Multilevel memory programming aspects
- G11C2211/5622—Concurrent multilevel programming of more than one cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5642—Multilevel memory with buffers, latches, registers at input or output
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5647—Multilevel memory with bit inversion arrangement
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US1996/010393 WO1997048101A1 (en) | 1996-06-14 | 1996-06-14 | Floating gate memory device with low current page buffer |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69633577D1 true DE69633577D1 (de) | 2004-11-11 |
DE69633577T2 DE69633577T2 (de) | 2005-10-13 |
Family
ID=22255336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69633577T Expired - Lifetime DE69633577T2 (de) | 1996-06-14 | 1996-06-14 | Schwebegatterspeicheranordnung mit seitenpuffer mit niedrigem strom |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0904589B1 (de) |
JP (1) | JP2000512057A (de) |
DE (1) | DE69633577T2 (de) |
WO (1) | WO1997048101A1 (de) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69923548D1 (de) * | 1999-06-22 | 2005-03-10 | St Microelectronics Srl | Flashkompatibler EEPROM Speicher |
FR2803080A1 (fr) * | 1999-12-22 | 2001-06-29 | St Microelectronics Sa | Memoire flash programmable page par page |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0713879B2 (ja) * | 1985-06-21 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
US5363330A (en) * | 1991-01-28 | 1994-11-08 | Mitsubishi Denki Kabushiki Kaisha | Non-volatile semiconductor memory device incorporating data latch and address counter for page mode programming |
US5357462A (en) * | 1991-09-24 | 1994-10-18 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller |
KR950000273B1 (ko) * | 1992-02-21 | 1995-01-12 | 삼성전자 주식회사 | 불휘발성 반도체 메모리장치 및 그 최적화 기입방법 |
US5323351A (en) * | 1992-06-10 | 1994-06-21 | Nexcom Technology, Inc. | Method and apparatus for programming electrical erasable programmable read-only memory arrays |
US5357463A (en) * | 1992-11-17 | 1994-10-18 | Micron Semiconductor, Inc. | Method for reverse programming of a flash EEPROM |
-
1996
- 1996-06-14 JP JP10501550A patent/JP2000512057A/ja active Pending
- 1996-06-14 WO PCT/US1996/010393 patent/WO1997048101A1/en active IP Right Grant
- 1996-06-14 EP EP96921634A patent/EP0904589B1/de not_active Expired - Lifetime
- 1996-06-14 DE DE69633577T patent/DE69633577T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
WO1997048101A1 (en) | 1997-12-18 |
EP0904589A1 (de) | 1999-03-31 |
EP0904589B1 (de) | 2004-10-06 |
DE69633577T2 (de) | 2005-10-13 |
EP0904589A4 (de) | 2000-07-12 |
JP2000512057A (ja) | 2000-09-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |