DE69629495D1 - Vereinheitlichter multifunktions-operationsverteiler für die ungeordnete befehlsexekution in einem superskalaren prozessor - Google Patents
Vereinheitlichter multifunktions-operationsverteiler für die ungeordnete befehlsexekution in einem superskalaren prozessorInfo
- Publication number
- DE69629495D1 DE69629495D1 DE69629495T DE69629495T DE69629495D1 DE 69629495 D1 DE69629495 D1 DE 69629495D1 DE 69629495 T DE69629495 T DE 69629495T DE 69629495 T DE69629495 T DE 69629495T DE 69629495 D1 DE69629495 D1 DE 69629495D1
- Authority
- DE
- Germany
- Prior art keywords
- uniformed
- disordered
- super
- command execution
- scalar processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
- G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Applications Claiming Priority (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US506995P | 1995-10-06 | 1995-10-06 | |
US5069P | 1995-10-06 | ||
US502195P | 1995-10-10 | 1995-10-10 | |
US5021P | 1995-10-10 | ||
US59038396A | 1996-01-26 | 1996-01-26 | |
US590383 | 1996-01-26 | ||
US649243 | 1996-05-16 | ||
US08/649,243 US5884059A (en) | 1996-01-26 | 1996-05-16 | Unified multi-function operation scheduler for out-of-order execution in a superscalar processor |
PCT/US1996/015743 WO1997013201A1 (en) | 1995-10-06 | 1996-10-04 | Unified multi-function operation scheduler for out-of-order execution in a superscalar processor |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69629495D1 true DE69629495D1 (de) | 2003-09-18 |
DE69629495T2 DE69629495T2 (de) | 2004-06-09 |
Family
ID=27485435
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69629495T Expired - Lifetime DE69629495T2 (de) | 1995-10-06 | 1996-10-04 | Vereinheitlichter multifunktions-operationsverteiler für die ungeordnete befehlsexekution in einem superskalaren prozessor |
Country Status (6)
Country | Link |
---|---|
US (1) | US6195744B1 (de) |
EP (1) | EP0870228B1 (de) |
JP (1) | JP3720371B2 (de) |
AU (1) | AU7550496A (de) |
DE (1) | DE69629495T2 (de) |
WO (1) | WO1997013201A1 (de) |
Families Citing this family (67)
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US5903741A (en) * | 1995-01-25 | 1999-05-11 | Advanced Micro Devices, Inc. | Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions |
US5901302A (en) * | 1995-01-25 | 1999-05-04 | Advanced Micro Devices, Inc. | Superscalar microprocessor having symmetrical, fixed issue positions each configured to execute a particular subset of instructions |
US5878244A (en) * | 1995-01-25 | 1999-03-02 | Advanced Micro Devices, Inc. | Reorder buffer configured to allocate storage capable of storing results corresponding to a maximum number of concurrently receivable instructions regardless of a number of instructions received |
US6237082B1 (en) | 1995-01-25 | 2001-05-22 | Advanced Micro Devices, Inc. | Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received |
US5915110A (en) * | 1996-07-26 | 1999-06-22 | Advanced Micro Devices, Inc. | Branch misprediction recovery in a reorder buffer having a future file |
US5946468A (en) * | 1996-07-26 | 1999-08-31 | Advanced Micro Devices, Inc. | Reorder buffer having an improved future file for storing speculative instruction execution results |
US5872951A (en) * | 1996-07-26 | 1999-02-16 | Advanced Micro Design, Inc. | Reorder buffer having a future file for storing speculative instruction execution results |
US5983342A (en) * | 1996-09-12 | 1999-11-09 | Advanced Micro Devices, Inc. | Superscalar microprocessor employing a future file for storing results into multiportion registers |
DE69725620T2 (de) * | 1997-08-06 | 2004-08-12 | Advanced Micro Devices, Inc., Sunnyvale | Vorrichtung und verfahren zum speziellen registerzugang ohne serialisation |
US6044453A (en) * | 1997-09-18 | 2000-03-28 | Lg Semicon Co., Ltd. | User programmable circuit and method for data processing apparatus using a self-timed asynchronous control structure |
US6055620A (en) * | 1997-09-18 | 2000-04-25 | Lg Semicon Co., Ltd. | Apparatus and method for system control using a self-timed asynchronous control structure |
US6334182B2 (en) * | 1998-08-18 | 2001-12-25 | Intel Corp | Scheduling operations using a dependency matrix |
US6329838B1 (en) * | 1999-03-09 | 2001-12-11 | Kabushiki Kaisha Toshiba | Logic circuits and carry-lookahead circuits |
EP1050799A1 (de) | 1999-05-03 | 2000-11-08 | STMicroelectronics S.A. | Ausführung eines Rechnerprogramms |
US6591343B1 (en) * | 2000-02-22 | 2003-07-08 | Ip-First, Llc | Predecode in parallel with TLB compare |
US7062767B1 (en) * | 2000-09-05 | 2006-06-13 | Raza Microelectronics, Inc. | Method for coordinating information flow between components |
US6754808B1 (en) * | 2000-09-29 | 2004-06-22 | Intel Corporation | Valid bit generation and tracking in a pipelined processor |
JP3709553B2 (ja) * | 2000-12-19 | 2005-10-26 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 演算回路および演算方法 |
JP3755415B2 (ja) * | 2001-04-04 | 2006-03-15 | 株式会社デンソー | 処理実行装置、当該処理実行装置に搭載される処理プログラム、及び記録媒体 |
US7269714B2 (en) | 2001-09-24 | 2007-09-11 | Broadcom Corporation | Inhibiting of a co-issuing instruction in a processor having different pipeline lengths |
US6976152B2 (en) * | 2001-09-24 | 2005-12-13 | Broadcom Corporation | Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard |
US7203817B2 (en) * | 2001-09-24 | 2007-04-10 | Broadcom Corporation | Power consumption reduction in a pipeline by stalling instruction issue on a load miss |
US7251594B2 (en) * | 2001-12-21 | 2007-07-31 | Hitachi, Ltd. | Execution time modification of instruction emulation parameters |
US7260217B1 (en) * | 2002-03-01 | 2007-08-21 | Cavium Networks, Inc. | Speculative execution for data ciphering operations |
US7085940B2 (en) * | 2002-05-09 | 2006-08-01 | International Business Machines Corporation | Floating point unit power reduction via inhibiting register file write during tight loop execution |
JP4283576B2 (ja) * | 2003-03-27 | 2009-06-24 | 株式会社日立製作所 | トランザクション同期方法、データベースシステム及びデータベース装置 |
US7555633B1 (en) | 2003-11-03 | 2009-06-30 | Advanced Micro Devices, Inc. | Instruction cache prefetch based on trace cache eviction |
US8069336B2 (en) * | 2003-12-03 | 2011-11-29 | Globalfoundries Inc. | Transitioning from instruction cache to trace cache on label boundaries |
US7197630B1 (en) | 2004-04-12 | 2007-03-27 | Advanced Micro Devices, Inc. | Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation |
US20060282821A1 (en) * | 2005-06-10 | 2006-12-14 | Renno Erik K | Efficient subprogram return in microprocessors |
GB2463278B (en) * | 2008-09-05 | 2012-05-16 | Advanced Risc Mach Ltd | Scheduling control within a data processing system |
US8103850B2 (en) * | 2009-05-05 | 2012-01-24 | International Business Machines Corporation | Dynamic translation in the presence of intermixed code and data |
US8055883B2 (en) * | 2009-07-01 | 2011-11-08 | Arm Limited | Pipe scheduling for pipelines based on destination register number |
US9176738B2 (en) * | 2011-01-12 | 2015-11-03 | Advanced Micro Devices, Inc. | Method and apparatus for fast decoding and enhancing execution speed of an instruction |
US8935574B2 (en) | 2011-12-16 | 2015-01-13 | Advanced Micro Devices, Inc. | Correlating traces in a computing system |
US8683296B2 (en) | 2011-12-30 | 2014-03-25 | Streamscale, Inc. | Accelerated erasure coding system and method |
US8914706B2 (en) | 2011-12-30 | 2014-12-16 | Streamscale, Inc. | Using parity data for concurrent data authentication, correction, compression, and encryption |
US9268569B2 (en) * | 2012-02-24 | 2016-02-23 | Apple Inc. | Branch misprediction behavior suppression on zero predicate branch mispredict |
US9087409B2 (en) * | 2012-03-01 | 2015-07-21 | Qualcomm Incorporated | Techniques for reducing memory access bandwidth in a graphics processing system based on destination alpha values |
US8966324B2 (en) | 2012-06-15 | 2015-02-24 | International Business Machines Corporation | Transactional execution branch indications |
US9772854B2 (en) | 2012-06-15 | 2017-09-26 | International Business Machines Corporation | Selectively controlling instruction execution in transactional processing |
US9448796B2 (en) | 2012-06-15 | 2016-09-20 | International Business Machines Corporation | Restricted instructions in transactional execution |
US20130339680A1 (en) | 2012-06-15 | 2013-12-19 | International Business Machines Corporation | Nontransactional store instruction |
US9740549B2 (en) | 2012-06-15 | 2017-08-22 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
US10437602B2 (en) | 2012-06-15 | 2019-10-08 | International Business Machines Corporation | Program interruption filtering in transactional execution |
US9442737B2 (en) | 2012-06-15 | 2016-09-13 | International Business Machines Corporation | Restricting processing within a processor to facilitate transaction completion |
US8682877B2 (en) | 2012-06-15 | 2014-03-25 | International Business Machines Corporation | Constrained transaction execution |
US8880959B2 (en) | 2012-06-15 | 2014-11-04 | International Business Machines Corporation | Transaction diagnostic block |
US9436477B2 (en) | 2012-06-15 | 2016-09-06 | International Business Machines Corporation | Transaction abort instruction |
US9317460B2 (en) | 2012-06-15 | 2016-04-19 | International Business Machines Corporation | Program event recording within a transactional environment |
US8688661B2 (en) | 2012-06-15 | 2014-04-01 | International Business Machines Corporation | Transactional processing |
US9348642B2 (en) | 2012-06-15 | 2016-05-24 | International Business Machines Corporation | Transaction begin/end instructions |
US9336046B2 (en) | 2012-06-15 | 2016-05-10 | International Business Machines Corporation | Transaction abort processing |
US9361115B2 (en) | 2012-06-15 | 2016-06-07 | International Business Machines Corporation | Saving/restoring selected registers in transactional processing |
US9367323B2 (en) | 2012-06-15 | 2016-06-14 | International Business Machines Corporation | Processor assist facility |
US9384004B2 (en) | 2012-06-15 | 2016-07-05 | International Business Machines Corporation | Randomized testing within transactional execution |
US8832500B2 (en) | 2012-08-10 | 2014-09-09 | Advanced Micro Devices, Inc. | Multiple clock domain tracing |
US8959398B2 (en) | 2012-08-16 | 2015-02-17 | Advanced Micro Devices, Inc. | Multiple clock domain debug capability |
US8972645B2 (en) * | 2012-09-19 | 2015-03-03 | Hewlett-Packard Development Company, L.P. | Request sent to storage device based on moving average |
JP6094356B2 (ja) * | 2013-04-22 | 2017-03-15 | 富士通株式会社 | 演算処理装置 |
US9710278B2 (en) * | 2014-09-30 | 2017-07-18 | International Business Machines Corporation | Optimizing grouping of instructions |
US9852202B1 (en) * | 2016-09-23 | 2017-12-26 | International Business Machines Corporation | Bandwidth-reduced coherency communication |
CN106406814B (zh) * | 2016-09-30 | 2019-06-14 | 上海兆芯集成电路有限公司 | 处理器和将架构指令转译成微指令的方法 |
KR20180038793A (ko) * | 2016-10-07 | 2018-04-17 | 삼성전자주식회사 | 영상 데이터 처리 방법 및 장치 |
JP6292324B2 (ja) * | 2017-01-05 | 2018-03-14 | 富士通株式会社 | 演算処理装置 |
US10360034B2 (en) | 2017-04-18 | 2019-07-23 | Samsung Electronics Co., Ltd. | System and method for maintaining data in a low-power structure |
US11256621B2 (en) | 2019-06-25 | 2022-02-22 | Seagate Technology Llc | Dual controller cache optimization in a deterministic data storage system |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
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US4807115A (en) | 1983-10-07 | 1989-02-21 | Cornell Research Foundation, Inc. | Instruction issuing mechanism for processors with multiple functional units |
US5136697A (en) | 1989-06-06 | 1992-08-04 | Advanced Micro Devices, Inc. | System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache |
GB9123271D0 (en) | 1991-11-02 | 1991-12-18 | Int Computers Ltd | Data processing system |
US5560025A (en) | 1993-03-31 | 1996-09-24 | Intel Corporation | Entry allocation apparatus and method of same |
US5454117A (en) | 1993-08-25 | 1995-09-26 | Nexgen, Inc. | Configurable branch prediction for a processor performing speculative execution |
US5519864A (en) | 1993-12-27 | 1996-05-21 | Intel Corporation | Method and apparatus for scheduling the dispatch of instructions from a reservation station |
US5546597A (en) | 1994-02-28 | 1996-08-13 | Intel Corporation | Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution |
US5555432A (en) | 1994-08-19 | 1996-09-10 | Intel Corporation | Circuit and method for scheduling instructions by predicting future availability of resources required for execution |
US5884059A (en) * | 1996-01-26 | 1999-03-16 | Advanced Micro Devices, Inc. | Unified multi-function operation scheduler for out-of-order execution in a superscalar processor |
US5761776A (en) | 1997-01-30 | 1998-06-09 | 532341 Ontario Inc. | Locking hook with integral separator |
US5858176A (en) | 1997-04-22 | 1999-01-12 | Betzdearborn Inc. | Compositions and methods for inhibiting fouling of vinyl monomers |
-
1996
- 1996-10-04 EP EP96937644A patent/EP0870228B1/de not_active Expired - Lifetime
- 1996-10-04 JP JP51437297A patent/JP3720371B2/ja not_active Expired - Fee Related
- 1996-10-04 DE DE69629495T patent/DE69629495T2/de not_active Expired - Lifetime
- 1996-10-04 AU AU75504/96A patent/AU7550496A/en not_active Abandoned
- 1996-10-04 WO PCT/US1996/015743 patent/WO1997013201A1/en active IP Right Grant
-
1999
- 1999-02-18 US US09/252,898 patent/US6195744B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0870228A1 (de) | 1998-10-14 |
EP0870228B1 (de) | 2003-08-13 |
DE69629495T2 (de) | 2004-06-09 |
WO1997013201A1 (en) | 1997-04-10 |
JPH11510291A (ja) | 1999-09-07 |
US6195744B1 (en) | 2001-02-27 |
AU7550496A (en) | 1997-04-28 |
JP3720371B2 (ja) | 2005-11-24 |
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