DE69619372D1 - Fehlererkennungs- und fehlerkorrekturverfahren - Google Patents

Fehlererkennungs- und fehlerkorrekturverfahren

Info

Publication number
DE69619372D1
DE69619372D1 DE69619372T DE69619372T DE69619372D1 DE 69619372 D1 DE69619372 D1 DE 69619372D1 DE 69619372 T DE69619372 T DE 69619372T DE 69619372 T DE69619372 T DE 69619372T DE 69619372 D1 DE69619372 D1 DE 69619372D1
Authority
DE
Germany
Prior art keywords
error detecting
corrective procedure
corrective
procedure
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69619372T
Other languages
English (en)
Other versions
DE69619372T2 (de
Inventor
Nirmal Saxena
David Chang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69619372D1 publication Critical patent/DE69619372D1/de
Application granted granted Critical
Publication of DE69619372T2 publication Critical patent/DE69619372T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Detection And Correction Of Errors (AREA)
DE69619372T 1995-06-05 1996-06-05 Fehlererkennungs- und fehlerkorrekturverfahren Expired - Lifetime DE69619372T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/465,367 US5533035A (en) 1993-06-16 1995-06-05 Error detection and correction method and apparatus
PCT/US1996/009041 WO1996039661A1 (en) 1995-06-05 1996-06-05 Error detection and correction method and apparatus

Publications (2)

Publication Number Publication Date
DE69619372D1 true DE69619372D1 (de) 2002-03-28
DE69619372T2 DE69619372T2 (de) 2002-07-11

Family

ID=23847530

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69619372T Expired - Lifetime DE69619372T2 (de) 1995-06-05 1996-06-05 Fehlererkennungs- und fehlerkorrekturverfahren

Country Status (5)

Country Link
US (1) US5533035A (de)
EP (1) EP0834125B1 (de)
JP (1) JP3741318B2 (de)
DE (1) DE69619372T2 (de)
WO (1) WO1996039661A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0993225A (ja) * 1995-09-27 1997-04-04 Kokusai Electric Co Ltd データ受信装置
US6119248A (en) * 1998-01-26 2000-09-12 Dell Usa L.P. Operating system notification of correctable error in computer information
US7509550B2 (en) * 2003-02-13 2009-03-24 Janusz Rajski Fault diagnosis of compressed test responses
WO2004072660A2 (en) * 2003-02-13 2004-08-26 Mentor Graphics Corporation Compressing test responses using a compactor
EP1460542B1 (de) * 2003-03-19 2018-10-31 Micron Technology, INC. Integriertes Speichersystem mit mindestens einem nichtflüchtigen Speicher und einem automatischen Fehlerkorrektor
JP2007064762A (ja) * 2005-08-30 2007-03-15 Matsushita Electric Ind Co Ltd 半導体装置、テストモード制御回路
US20080052598A1 (en) * 2006-08-09 2008-02-28 Aksamit Slavek P Memory multi-bit error correction and hot replace without mirroring
US7730346B2 (en) * 2007-04-30 2010-06-01 Globalfoundries Inc. Parallel instruction processing and operand integrity verification
TW200906072A (en) * 2007-07-24 2009-02-01 Princeton Technology Corp Error-correcting method used in decoding of data transmitting
CN102099793B (zh) * 2008-06-24 2013-10-16 桑迪士克以色列有限公司 根据固态存储器的擦除计数进行误差校正的方法和装置
JP5202130B2 (ja) 2008-06-24 2013-06-05 株式会社東芝 キャッシュメモリ、コンピュータシステム、及びメモリアクセス方法
US8694750B2 (en) * 2008-12-19 2014-04-08 Nvidia Corporation Method and system for data structure management
US9208108B2 (en) * 2008-12-19 2015-12-08 Nvidia Corporation Method and system for improved flash controller commands selection
US8732350B2 (en) * 2008-12-19 2014-05-20 Nvidia Corporation Method and system for improving direct memory access offload
US8683293B2 (en) * 2009-12-16 2014-03-25 Nvidia Corporation Method and system for fast two bit error correction
US20110161553A1 (en) * 2009-12-30 2011-06-30 Nvidia Corporation Memory device wear-leveling techniques
US9594675B2 (en) * 2009-12-31 2017-03-14 Nvidia Corporation Virtualization of chip enables
US9465728B2 (en) 2010-11-03 2016-10-11 Nvidia Corporation Memory controller adaptable to multiple memory devices
US8533557B2 (en) 2011-01-28 2013-09-10 Infineon Technologies Ag Device and method for error correction and protection against data corruption
US9218289B2 (en) * 2012-08-06 2015-12-22 Qualcomm Incorporated Multi-core compute cache coherency with a release consistency memory ordering model
US8954832B1 (en) * 2012-09-05 2015-02-10 L-3 Communications Corp. Asymmetric distance coding
US9658920B1 (en) 2013-06-21 2017-05-23 Altera Corporation Method for reconfiguring an erroneous memory frame in an integrated circuit
DE102015112554B4 (de) * 2015-07-30 2017-10-26 Hochschule Nordhausen Verfahren und Vorrichtung zum Erzeugen einer Codebitsequenz sowie zum Erkennen von Bitfehlern

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3685014A (en) * 1970-10-09 1972-08-15 Ibm Automatic double error detection and correction device
US3656107A (en) * 1970-10-23 1972-04-11 Ibm Automatic double error detection and correction apparatus
US3714629A (en) * 1971-06-01 1973-01-30 Ibm Double error correcting method and system
US4139148A (en) * 1977-08-25 1979-02-13 Sperry Rand Corporation Double bit error correction using single bit error correction, double bit error detection logic and syndrome bit memory
US4163147A (en) * 1978-01-20 1979-07-31 Sperry Rand Corporation Double bit error correction using double bit complementing
US4637021A (en) * 1983-09-28 1987-01-13 Pioneer Electronic Corporation Multiple pass error correction
US5051999A (en) * 1989-03-13 1991-09-24 Motorola, Inc. Programmable error correcting apparatus within a paging receiver

Also Published As

Publication number Publication date
JP3741318B2 (ja) 2006-02-01
US5533035A (en) 1996-07-02
DE69619372T2 (de) 2002-07-11
JP2001504251A (ja) 2001-03-27
EP0834125A1 (de) 1998-04-08
EP0834125B1 (de) 2002-02-20
WO1996039661A1 (en) 1996-12-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

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