DE69617263D1 - Neue seitenwand-metall-passivierungs-technologie für subhalbmikrometer-integrierte schaltungsanwendungen - Google Patents

Neue seitenwand-metall-passivierungs-technologie für subhalbmikrometer-integrierte schaltungsanwendungen

Info

Publication number
DE69617263D1
DE69617263D1 DE69617263T DE69617263T DE69617263D1 DE 69617263 D1 DE69617263 D1 DE 69617263D1 DE 69617263 T DE69617263 T DE 69617263T DE 69617263 T DE69617263 T DE 69617263T DE 69617263 D1 DE69617263 D1 DE 69617263D1
Authority
DE
Germany
Prior art keywords
side wall
integrated circuit
wall metal
new side
circuit applications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69617263T
Other languages
English (en)
Other versions
DE69617263T2 (de
Inventor
W Cheung
S Chan
Subhash Gupta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69617263D1 publication Critical patent/DE69617263D1/de
Publication of DE69617263T2 publication Critical patent/DE69617263T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69617263T 1995-11-29 1996-09-18 Neue seitenwand-metall-passivierungs-technologie für subhalbmikrometer-integrierte schaltungsanwendungen Expired - Fee Related DE69617263T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/564,752 US5814560A (en) 1995-11-29 1995-11-29 Metallization sidewall passivation technology for deep sub-half micrometer IC applications
PCT/US1996/014932 WO1997020346A1 (en) 1995-11-29 1996-09-18 Novel metallization sidewall passivation technology for deep sub-half micrometer ic applications

Publications (2)

Publication Number Publication Date
DE69617263D1 true DE69617263D1 (de) 2002-01-03
DE69617263T2 DE69617263T2 (de) 2002-07-18

Family

ID=24255736

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69617263T Expired - Fee Related DE69617263T2 (de) 1995-11-29 1996-09-18 Neue seitenwand-metall-passivierungs-technologie für subhalbmikrometer-integrierte schaltungsanwendungen

Country Status (6)

Country Link
US (1) US5814560A (de)
EP (1) EP0864175B1 (de)
JP (1) JP2000501240A (de)
KR (1) KR100404764B1 (de)
DE (1) DE69617263T2 (de)
WO (1) WO1997020346A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6355983B2 (en) * 1997-05-20 2002-03-12 Texas Instruments Incorporated Surface modified interconnects
US20010055868A1 (en) 1998-05-22 2001-12-27 Madan Sudhir K. Apparatus and method for metal layer streched conducting plugs
US6071808A (en) * 1999-06-23 2000-06-06 Lucent Technologies Inc. Method of passivating copper interconnects in a semiconductor
US6650043B1 (en) * 1999-07-20 2003-11-18 Micron Technology, Inc. Multilayer conductor structure for use in field emission display
US6358788B1 (en) 1999-08-30 2002-03-19 Micron Technology, Inc. Method of fabricating a wordline in a memory array of a semiconductor device
US6995392B2 (en) * 2002-08-07 2006-02-07 International Business Machines Corporation Test structure for locating electromigration voids in dual damascene interconnects
US7498257B2 (en) * 2006-01-11 2009-03-03 Macronix International Co., Ltd. Methods for metal ARC layer formation
KR20180068595A (ko) * 2016-12-14 2018-06-22 삼성전자주식회사 반도체 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817557A (en) * 1983-05-23 1989-04-04 Anicon, Inc. Process and apparatus for low pressure chemical vapor deposition of refractory metal
US4980752A (en) * 1986-12-29 1990-12-25 Inmos Corporation Transition metal clad interconnect for integrated circuits
KR920005701B1 (ko) * 1989-07-20 1992-07-13 현대전자산업 주식회사 반도체 집적회로 내의 소자 연결용 금속배선층 및 그 제조방법
JPH04346231A (ja) * 1991-05-23 1992-12-02 Canon Inc 半導体装置の製造方法
US5462892A (en) * 1992-06-22 1995-10-31 Vlsi Technology, Inc. Semiconductor processing method for preventing corrosion of metal film connections
JPH06117118A (ja) * 1992-10-09 1994-04-26 Fujita Corp 開閉式全天候型仮設屋根構造
US5358901A (en) * 1993-03-01 1994-10-25 Motorola, Inc. Process for forming an intermetallic layer
US5571751A (en) * 1994-05-09 1996-11-05 National Semiconductor Corporation Interconnect structures for integrated circuits
US5604155A (en) * 1995-07-17 1997-02-18 Winbond Electronics Corp. Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging

Also Published As

Publication number Publication date
DE69617263T2 (de) 2002-07-18
US5814560A (en) 1998-09-29
EP0864175A1 (de) 1998-09-16
KR100404764B1 (ko) 2003-12-18
EP0864175B1 (de) 2001-11-21
JP2000501240A (ja) 2000-02-02
WO1997020346A1 (en) 1997-06-05
KR19990071719A (ko) 1999-09-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee