DE69615616D1 - Verfahren und Anordnung zur Überwachung von Ressourcenzuteilung innerhalb eines Prozessors - Google Patents

Verfahren und Anordnung zur Überwachung von Ressourcenzuteilung innerhalb eines Prozessors

Info

Publication number
DE69615616D1
DE69615616D1 DE69615616T DE69615616T DE69615616D1 DE 69615616 D1 DE69615616 D1 DE 69615616D1 DE 69615616 T DE69615616 T DE 69615616T DE 69615616 T DE69615616 T DE 69615616T DE 69615616 D1 DE69615616 D1 DE 69615616D1
Authority
DE
Germany
Prior art keywords
processor
arrangement
resource allocation
monitoring resource
monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69615616T
Other languages
English (en)
Inventor
Kin Chan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69615616D1 publication Critical patent/DE69615616D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384Register renaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858Result writeback, i.e. updating the architectural state or memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE69615616T 1995-06-29 1996-05-31 Verfahren und Anordnung zur Überwachung von Ressourcenzuteilung innerhalb eines Prozessors Expired - Lifetime DE69615616D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/496,833 US5809268A (en) 1995-06-29 1995-06-29 Method and system for tracking resource allocation within a processor

Publications (1)

Publication Number Publication Date
DE69615616D1 true DE69615616D1 (de) 2001-11-08

Family

ID=23974348

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615616T Expired - Lifetime DE69615616D1 (de) 1995-06-29 1996-05-31 Verfahren und Anordnung zur Überwachung von Ressourcenzuteilung innerhalb eines Prozessors

Country Status (5)

Country Link
US (1) US5809268A (de)
EP (1) EP0751458B1 (de)
JP (1) JP3093639B2 (de)
KR (1) KR100225244B1 (de)
DE (1) DE69615616D1 (de)

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US7188232B1 (en) * 2000-05-03 2007-03-06 Choquette Jack H Pipelined processing with commit speculation staging buffer and load/store centric exception handling
US6675372B1 (en) * 2000-10-31 2004-01-06 Sun Microsystems, Inc. Counting speculative and non-speculative events
US20040186982A9 (en) * 2002-02-06 2004-09-23 Matthew Becker Stalling Instructions in a pipelined microprocessor
US6912633B2 (en) 2002-03-18 2005-06-28 Sun Microsystems, Inc. Enhanced memory management for portable devices
US6996802B2 (en) 2002-03-18 2006-02-07 Sun Microsystems, Inc. Method and apparatus for deployment of high integrity software using initialization order and calling order constraints
US7181737B2 (en) 2002-03-18 2007-02-20 Sun Microsystems, Inc. Method and apparatus for deployment of high integrity software using static procedure return addresses
US7010783B2 (en) 2002-03-18 2006-03-07 Sun Microsystems, Inc. Method and apparatus for deployment of high integrity software using reduced dynamic memory allocation
US7281237B2 (en) 2003-01-16 2007-10-09 Sun Microsystems, Inc. Run-time verification of annotated software code
US7657893B2 (en) 2003-04-23 2010-02-02 International Business Machines Corporation Accounting method and logic for determining per-thread processor resource utilization in a simultaneous multi-threaded (SMT) processor
US7424620B2 (en) 2003-09-25 2008-09-09 Sun Microsystems, Inc. Interleaved data and instruction streams for application program obfuscation
US8220058B2 (en) 2003-09-25 2012-07-10 Oracle America, Inc. Rendering and encryption engine for application program obfuscation
US7363620B2 (en) 2003-09-25 2008-04-22 Sun Microsystems, Inc. Non-linear execution of application program instructions for application program obfuscation
US7353499B2 (en) 2003-09-25 2008-04-01 Sun Microsystems, Inc. Multiple instruction dispatch tables for application program obfuscation
US7415618B2 (en) 2003-09-25 2008-08-19 Sun Microsystems, Inc. Permutation of opcode values for application program obfuscation
US8190863B2 (en) * 2004-07-02 2012-05-29 Intel Corporation Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction
US20060026388A1 (en) * 2004-07-30 2006-02-02 Karp Alan H Computer executing instructions having embedded synchronization points
JP4276201B2 (ja) * 2005-03-31 2009-06-10 富士通株式会社 Smtプロセッサ用課金処理装置,課金処理方法,および課金処理プログラム
US8161493B2 (en) 2008-07-15 2012-04-17 International Business Machines Corporation Weighted-region cycle accounting for multi-threaded processor cores
US9690625B2 (en) * 2009-06-16 2017-06-27 Oracle America, Inc. System and method for out-of-order resource allocation and deallocation in a threaded machine
US8776061B2 (en) * 2010-12-16 2014-07-08 International Business Machines Corporation Real-time distributed monitoring of local and global processor resource allocations and deallocations
US9229791B1 (en) * 2012-08-24 2016-01-05 Qlogic, Corporation System and method for high speed multiple buffer allocation
US9448800B2 (en) * 2013-03-14 2016-09-20 Samsung Electronics Co., Ltd. Reorder-buffer-based static checkpointing for rename table rebuilding
US11263047B2 (en) * 2018-02-15 2022-03-01 Sap Se Metadata management for multi-core resource manager
US10929139B2 (en) 2018-09-27 2021-02-23 Qualcomm Incorporated Providing predictive instruction dispatch throttling to prevent resource overflows in out-of-order processor (OOP)-based devices
US11086630B1 (en) 2020-02-27 2021-08-10 International Business Machines Corporation Finish exception handling of an instruction completion table
US11829762B2 (en) 2022-01-30 2023-11-28 Simplex Micro, Inc. Time-resource matrix for a microprocessor with time counter for statically dispatching instructions
US11829187B2 (en) 2022-01-30 2023-11-28 Simplex Micro, Inc. Microprocessor with time counter for statically dispatching instructions
US11829767B2 (en) 2022-01-30 2023-11-28 Simplex Micro, Inc. Register scoreboard for a microprocessor with a time counter for statically dispatching instructions
US12001848B2 (en) 2022-01-30 2024-06-04 Simplex Micro, Inc. Microprocessor with time counter for statically dispatching instructions with phantom registers
US11954491B2 (en) 2022-01-30 2024-04-09 Simplex Micro, Inc. Multi-threading microprocessor with a time counter for statically dispatching instructions
US20230315474A1 (en) * 2022-04-05 2023-10-05 Simplex Micro, Inc. Microprocessor with apparatus and method for replaying instructions
US12106114B2 (en) 2022-04-29 2024-10-01 Simplex Micro, Inc. Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter
US12112172B2 (en) 2022-06-01 2024-10-08 Simplex Micro, Inc. Vector coprocessor with time counter for statically dispatching instructions

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Also Published As

Publication number Publication date
KR100225244B1 (ko) 1999-10-15
US5809268A (en) 1998-09-15
JP3093639B2 (ja) 2000-10-03
EP0751458A1 (de) 1997-01-02
JPH09120359A (ja) 1997-05-06
EP0751458B1 (de) 2001-10-04

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