DE69534659D1 - Architektur und Verbindungsmodel für programmierbare logische Schaltungen - Google Patents
Architektur und Verbindungsmodel für programmierbare logische SchaltungenInfo
- Publication number
- DE69534659D1 DE69534659D1 DE69534659T DE69534659T DE69534659D1 DE 69534659 D1 DE69534659 D1 DE 69534659D1 DE 69534659 T DE69534659 T DE 69534659T DE 69534659 T DE69534659 T DE 69534659T DE 69534659 D1 DE69534659 D1 DE 69534659D1
- Authority
- DE
- Germany
- Prior art keywords
- routing network
- network lines
- layer
- connectability
- provide connectability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
- H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US22992394A | 1994-04-14 | 1994-04-14 | |
US229923 | 1994-04-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69534659D1 true DE69534659D1 (de) | 2006-01-05 |
DE69534659T2 DE69534659T2 (de) | 2006-09-07 |
Family
ID=22863228
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69534659T Expired - Lifetime DE69534659T2 (de) | 1994-04-14 | 1995-04-14 | Architektur und Verbindungsmodel für programmierbare logische Schaltungen |
DE69525741T Expired - Lifetime DE69525741D1 (de) | 1994-04-14 | 1995-04-14 | Architektur und verbindungsschema für programmierbare logische schaltungen |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69525741T Expired - Lifetime DE69525741D1 (de) | 1994-04-14 | 1995-04-14 | Architektur und verbindungsschema für programmierbare logische schaltungen |
Country Status (7)
Country | Link |
---|---|
EP (4) | EP1162746B1 (de) |
JP (1) | JP3581152B2 (de) |
CN (1) | CN1101082C (de) |
AT (1) | ATE214210T1 (de) |
AU (1) | AU2291495A (de) |
DE (2) | DE69534659T2 (de) |
WO (1) | WO1995028769A1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5457410A (en) | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
GB2305759A (en) * | 1995-09-30 | 1997-04-16 | Pilkington Micro Electronics | Semi-conductor integrated circuit |
EP0913032A4 (de) * | 1996-03-29 | 2001-03-14 | Dyna Logic Corp | Programmbierbare hochgeschwindigkeits-architektur |
US6034547A (en) * | 1996-09-04 | 2000-03-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus |
US6624658B2 (en) | 1999-02-04 | 2003-09-23 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US6300794B1 (en) | 1996-10-10 | 2001-10-09 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US5999016A (en) * | 1996-10-10 | 1999-12-07 | Altera Corporation | Architectures for programmable logic devices |
US5977793A (en) * | 1996-10-10 | 1999-11-02 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6107825A (en) * | 1997-10-16 | 2000-08-22 | Altera Corporation | Input/output circuitry for programmable logic devices |
US7389487B1 (en) | 1998-04-28 | 2008-06-17 | Actel Corporation | Dedicated interface architecture for a hybrid integrated circuit |
US7084476B2 (en) * | 2004-02-26 | 2006-08-01 | International Business Machines Corp. | Integrated circuit logic with self compensating block delays |
US6975139B2 (en) | 2004-03-30 | 2005-12-13 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US7460529B2 (en) | 2004-07-29 | 2008-12-02 | Advantage Logic, Inc. | Interconnection fabric using switching networks in hierarchy |
US7423453B1 (en) | 2006-01-20 | 2008-09-09 | Advantage Logic, Inc. | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
US7456653B2 (en) * | 2007-03-09 | 2008-11-25 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
US7999570B2 (en) | 2009-06-24 | 2011-08-16 | Advantage Logic, Inc. | Enhanced permutable switching network with multicasting signals for interconnection fabric |
CN102288903B (zh) * | 2011-07-26 | 2014-12-10 | 北京航空航天大学 | 一种fpga内连线资源的测试结构及方法 |
CN108427829B (zh) * | 2018-02-09 | 2022-11-08 | 京微齐力(北京)科技有限公司 | 一种具有公共线结构的fpga |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212652A (en) * | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
US5317209A (en) * | 1991-08-29 | 1994-05-31 | National Semiconductor Corporation | Dynamic three-state bussing capability in a configurable logic array |
GB9223226D0 (en) * | 1992-11-05 | 1992-12-16 | Algotronix Ltd | Improved configurable cellular array (cal ii) |
GB9312674D0 (en) * | 1993-06-18 | 1993-08-04 | Pilkington Micro Electronics | Configurabel logic array |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
-
1995
- 1995-04-14 JP JP52711795A patent/JP3581152B2/ja not_active Expired - Fee Related
- 1995-04-14 WO PCT/US1995/004639 patent/WO1995028769A1/en active IP Right Grant
- 1995-04-14 EP EP01119441A patent/EP1162746B1/de not_active Expired - Lifetime
- 1995-04-14 EP EP95916402A patent/EP0755588B1/de not_active Expired - Lifetime
- 1995-04-14 EP EP05015294A patent/EP1594228A3/de not_active Withdrawn
- 1995-04-14 EP EP01118849A patent/EP1162745A3/de not_active Withdrawn
- 1995-04-14 CN CN95193431.7A patent/CN1101082C/zh not_active Expired - Fee Related
- 1995-04-14 AT AT95916402T patent/ATE214210T1/de not_active IP Right Cessation
- 1995-04-14 AU AU22914/95A patent/AU2291495A/en not_active Abandoned
- 1995-04-14 DE DE69534659T patent/DE69534659T2/de not_active Expired - Lifetime
- 1995-04-14 DE DE69525741T patent/DE69525741D1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH10501934A (ja) | 1998-02-17 |
CN1101082C (zh) | 2003-02-05 |
EP1594228A3 (de) | 2005-11-16 |
EP0755588B1 (de) | 2002-03-06 |
EP1594228A2 (de) | 2005-11-09 |
WO1995028769A1 (en) | 1995-10-26 |
EP1162746A3 (de) | 2003-05-14 |
AU2291495A (en) | 1995-11-10 |
DE69534659T2 (de) | 2006-09-07 |
EP1162745A2 (de) | 2001-12-12 |
ATE214210T1 (de) | 2002-03-15 |
EP1162746B1 (de) | 2005-11-30 |
EP0755588A1 (de) | 1997-01-29 |
DE69525741D1 (de) | 2002-04-11 |
EP1162745A3 (de) | 2003-05-14 |
CN1152375A (zh) | 1997-06-18 |
EP1162746A2 (de) | 2001-12-12 |
JP3581152B2 (ja) | 2004-10-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: ACTEL CORP., MOUNTAIN VIEW, CALIF., US |