ATE214210T1 - Architektur und verbindungsschema für programmierbare logische schaltungen - Google Patents

Architektur und verbindungsschema für programmierbare logische schaltungen

Info

Publication number
ATE214210T1
ATE214210T1 AT95916402T AT95916402T ATE214210T1 AT E214210 T1 ATE214210 T1 AT E214210T1 AT 95916402 T AT95916402 T AT 95916402T AT 95916402 T AT95916402 T AT 95916402T AT E214210 T1 ATE214210 T1 AT E214210T1
Authority
AT
Austria
Prior art keywords
routing network
network lines
layer
connectability
provide connectability
Prior art date
Application number
AT95916402T
Other languages
English (en)
Inventor
Benjamin S Ting
Original Assignee
Btr Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Btr Inc filed Critical Btr Inc
Application granted granted Critical
Publication of ATE214210T1 publication Critical patent/ATE214210T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)
AT95916402T 1994-04-14 1995-04-14 Architektur und verbindungsschema für programmierbare logische schaltungen ATE214210T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US22992394A 1994-04-14 1994-04-14
PCT/US1995/004639 WO1995028769A1 (en) 1994-04-14 1995-04-14 Architecture and interconnect scheme for programmable logic circuits

Publications (1)

Publication Number Publication Date
ATE214210T1 true ATE214210T1 (de) 2002-03-15

Family

ID=22863228

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95916402T ATE214210T1 (de) 1994-04-14 1995-04-14 Architektur und verbindungsschema für programmierbare logische schaltungen

Country Status (7)

Country Link
EP (4) EP0755588B1 (de)
JP (1) JP3581152B2 (de)
CN (1) CN1101082C (de)
AT (1) ATE214210T1 (de)
AU (1) AU2291495A (de)
DE (2) DE69534659T2 (de)
WO (1) WO1995028769A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5457410A (en) 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits
GB2305759A (en) * 1995-09-30 1997-04-16 Pilkington Micro Electronics Semi-conductor integrated circuit
JP3774234B2 (ja) * 1996-03-29 2006-05-10 ザイリンクス， インコーポレイテッド 高速プログラマブルロジックアーキテクチャ
US6034547A (en) * 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
US6624658B2 (en) 1999-02-04 2003-09-23 Advantage Logic, Inc. Method and apparatus for universal program controlled bus architecture
US5977793A (en) * 1996-10-10 1999-11-02 Altera Corporation Programmable logic device with hierarchical interconnection resources
US6300794B1 (en) 1996-10-10 2001-10-09 Altera Corporation Programmable logic device with hierarchical interconnection resources
US5999016A (en) * 1996-10-10 1999-12-07 Altera Corporation Architectures for programmable logic devices
US6107825A (en) * 1997-10-16 2000-08-22 Altera Corporation Input/output circuitry for programmable logic devices
US7389487B1 (en) 1998-04-28 2008-06-17 Actel Corporation Dedicated interface architecture for a hybrid integrated circuit
US7084476B2 (en) * 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US6975139B2 (en) 2004-03-30 2005-12-13 Advantage Logic, Inc. Scalable non-blocking switching network for programmable logic
US7460529B2 (en) 2004-07-29 2008-12-02 Advantage Logic, Inc. Interconnection fabric using switching networks in hierarchy
US7423453B1 (en) 2006-01-20 2008-09-09 Advantage Logic, Inc. Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric
US7456653B2 (en) * 2007-03-09 2008-11-25 Altera Corporation Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks
US7999570B2 (en) 2009-06-24 2011-08-16 Advantage Logic, Inc. Enhanced permutable switching network with multicasting signals for interconnection fabric
CN102288903B (zh) * 2011-07-26 2014-12-10 北京航空航天大学 一种fpga内连线资源的测试结构及方法
CN108427829B (zh) * 2018-02-09 2022-11-08 京微齐力(北京)科技有限公司 一种具有公共线结构的fpga

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5338984A (en) * 1991-08-29 1994-08-16 National Semiconductor Corp. Local and express diagonal busses in a configurable logic array
GB9223226D0 (en) * 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
GB9312674D0 (en) * 1993-06-18 1993-08-04 Pilkington Micro Electronics Configurabel logic array
US5457410A (en) * 1993-08-03 1995-10-10 Btr, Inc. Architecture and interconnect scheme for programmable logic circuits

Also Published As

Publication number Publication date
EP1594228A3 (de) 2005-11-16
JP3581152B2 (ja) 2004-10-27
WO1995028769A1 (en) 1995-10-26
EP1162745A2 (de) 2001-12-12
DE69534659T2 (de) 2006-09-07
EP1162746B1 (de) 2005-11-30
EP1594228A2 (de) 2005-11-09
CN1152375A (zh) 1997-06-18
AU2291495A (en) 1995-11-10
JPH10501934A (ja) 1998-02-17
EP1162746A3 (de) 2003-05-14
EP0755588B1 (de) 2002-03-06
DE69525741D1 (de) 2002-04-11
EP1162745A3 (de) 2003-05-14
CN1101082C (zh) 2003-02-05
EP0755588A1 (de) 1997-01-29
EP1162746A2 (de) 2001-12-12
DE69534659D1 (de) 2006-01-05

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