DE69526006D1 - Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen - Google Patents

Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen

Info

Publication number
DE69526006D1
DE69526006D1 DE69526006T DE69526006T DE69526006D1 DE 69526006 D1 DE69526006 D1 DE 69526006D1 DE 69526006 T DE69526006 T DE 69526006T DE 69526006 T DE69526006 T DE 69526006T DE 69526006 D1 DE69526006 D1 DE 69526006D1
Authority
DE
Germany
Prior art keywords
integrated circuits
linear conductors
single twist
region arrangement
twist region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69526006T
Other languages
English (en)
Other versions
DE69526006T2 (de
Inventor
John Kenneth Debrosse
Jenifer Edith Lary
Edmund Juris Sprogis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69526006D1 publication Critical patent/DE69526006D1/de
Application granted granted Critical
Publication of DE69526006T2 publication Critical patent/DE69526006T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69526006T 1994-08-15 1995-07-13 Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen Expired - Fee Related DE69526006T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US29040894A 1994-08-15 1994-08-15

Publications (2)

Publication Number Publication Date
DE69526006D1 true DE69526006D1 (de) 2002-05-02
DE69526006T2 DE69526006T2 (de) 2003-01-02

Family

ID=23115860

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69526006T Expired - Fee Related DE69526006T2 (de) 1994-08-15 1995-07-13 Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen

Country Status (5)

Country Link
US (1) US5534732A (de)
EP (1) EP0697735B1 (de)
JP (1) JP3158017B2 (de)
KR (1) KR100187875B1 (de)
DE (1) DE69526006T2 (de)

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US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
US6043562A (en) * 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
JPH10107208A (ja) * 1996-09-30 1998-04-24 Toshiba Corp 半導体集積回路装置
US5847986A (en) * 1997-12-17 1998-12-08 Siemens Aktiengesellschaft Memory array with reduced charging current
US6034879A (en) * 1998-02-19 2000-03-07 University Of Pittsburgh Twisted line techniques for multi-gigabit dynamic random access memories
US5949698A (en) * 1998-02-20 1999-09-07 Micron Technology, Inc. Twisted global column decoder
US6249452B1 (en) * 1998-09-28 2001-06-19 Texas Instruments Incorporated Semiconductor device having offset twisted bit lines
US6326695B1 (en) * 1998-09-29 2001-12-04 Texas Instruments Incorporated Twisted bit line structures and method for making same
DE19907176A1 (de) * 1999-02-19 2000-08-31 Siemens Ag Decoder-Anschlußanordnung für Speicherchips mit langen Bitleitungen
JP2000269339A (ja) * 1999-03-16 2000-09-29 Toshiba Corp 半導体集積回路装置とその配線配置方法
US6504246B2 (en) * 1999-10-12 2003-01-07 Motorola, Inc. Integrated circuit having a balanced twist for differential signal lines
KR100326944B1 (ko) * 2000-01-10 2002-03-13 윤종용 향상된 입/출력 라인 구조를 갖는 반도체 메모리 장치
US7259464B1 (en) * 2000-05-09 2007-08-21 Micron Technology, Inc. Vertical twist scheme for high-density DRAMs
US7184290B1 (en) 2000-06-28 2007-02-27 Marvell International Ltd. Logic process DRAM
US6947324B1 (en) 2000-06-28 2005-09-20 Marvell International Ltd. Logic process DRAM
US6570781B1 (en) 2000-06-28 2003-05-27 Marvell International Ltd. Logic process DRAM
US6259621B1 (en) * 2000-07-06 2001-07-10 Micron Technology, Inc. Method and apparatus for minimization of data line coupling in a semiconductor memory device
KR100380387B1 (ko) * 2001-02-08 2003-04-11 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 신호 라인 배치 방법
US6742170B2 (en) 2001-12-28 2004-05-25 Intel Corporation Repeatable swizzling patterns for capacitive and inductive noise cancellation
US6848093B2 (en) * 2001-12-28 2005-01-25 Intel Corporation Interconnect swizzling for capacitive and inductive noise cancellation
US6563727B1 (en) * 2002-07-31 2003-05-13 Alan Roth Method and structure for reducing noise effects in content addressable memories
US7129935B2 (en) * 2003-06-02 2006-10-31 Synaptics Incorporated Sensor patterns for a capacitive sensing apparatus
KR100541818B1 (ko) * 2003-12-18 2006-01-10 삼성전자주식회사 반도체 메모리 장치의 라인 배치구조
US20050180053A1 (en) * 2004-02-18 2005-08-18 Headway Technologies, Inc. Cross talk and EME minimizing suspension design
US7139993B2 (en) * 2004-03-26 2006-11-21 Sun Microsystems, Inc. Method and apparatus for routing differential signals across a semiconductor chip
US7319602B1 (en) * 2004-07-01 2008-01-15 Netlogic Microsystems, Inc Content addressable memory with twisted data lines
JP5296963B2 (ja) * 2005-12-21 2013-09-25 エルピーダメモリ株式会社 多層配線半導体集積回路、半導体装置
JP2007189090A (ja) * 2006-01-13 2007-07-26 Renesas Technology Corp 半導体装置
US7464359B2 (en) * 2006-03-27 2008-12-09 International Business Machines Corporation Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure
US7830221B2 (en) * 2008-01-25 2010-11-09 Micron Technology, Inc. Coupling cancellation scheme
JP2009260158A (ja) * 2008-04-21 2009-11-05 Toshiba Corp 半導体集積回路装置における配線方法及び半導体集積回路装置
JP2009302132A (ja) * 2008-06-10 2009-12-24 Toshiba Corp レイアウト設計方法及び記録媒体
US20100044093A1 (en) * 2008-08-25 2010-02-25 Wilinx Corporation Layout geometries for differential signals
US7944724B2 (en) * 2009-04-28 2011-05-17 Netlogic Microsystems, Inc. Ternary content addressable memory having reduced leakage effects
US8411479B2 (en) * 2009-07-23 2013-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuits, systems, and methods for routing the memory circuits
US7920397B1 (en) 2010-04-30 2011-04-05 Netlogic Microsystems, Inc. Memory device having bit line leakage compensation

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1305255C (en) * 1986-08-25 1992-07-14 Joseph Lebowitz Marching interconnecting lines in semiconductor integrated circuits
JP2682021B2 (ja) * 1988-06-29 1997-11-26 富士通株式会社 半導体メモリ装置
US5144583A (en) * 1989-01-09 1992-09-01 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device with twisted bit-line structure
JPH02193393A (ja) * 1989-01-23 1990-07-31 Sharp Corp 半導体記憶装置
KR920010344B1 (ko) * 1989-12-29 1992-11-27 삼성전자주식회사 반도체 메모리 어레이의 구성방법
FR2668640A1 (fr) * 1990-10-30 1992-04-30 Samsung Electronics Co Ltd Memoire a semi-conducteurs possedant des lignes de bit et des lignes de mot qui se croisent.
US5287322A (en) * 1991-07-17 1994-02-15 Sgs-Thomson Microelectronics, Inc. Integrated circuit dual-port memory device having reduced capacitance

Also Published As

Publication number Publication date
US5534732A (en) 1996-07-09
JP3158017B2 (ja) 2001-04-23
KR100187875B1 (ko) 1999-06-01
DE69526006T2 (de) 2003-01-02
EP0697735B1 (de) 2002-03-27
JPH0870099A (ja) 1996-03-12
EP0697735A1 (de) 1996-02-21
KR960009059A (ko) 1996-03-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee