DE69520580D1 - Hierarchische Speicheranordnung - Google Patents

Hierarchische Speicheranordnung

Info

Publication number
DE69520580D1
DE69520580D1 DE69520580T DE69520580T DE69520580D1 DE 69520580 D1 DE69520580 D1 DE 69520580D1 DE 69520580 T DE69520580 T DE 69520580T DE 69520580 T DE69520580 T DE 69520580T DE 69520580 D1 DE69520580 D1 DE 69520580D1
Authority
DE
Germany
Prior art keywords
storage arrangement
hierarchical storage
hierarchical
arrangement
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69520580T
Other languages
English (en)
Other versions
DE69520580T2 (de
Inventor
Luigi Pascucci
Paolo Rolandi
Marco Fontana
Antonio Barcella
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69520580D1 publication Critical patent/DE69520580D1/de
Application granted granted Critical
Publication of DE69520580T2 publication Critical patent/DE69520580T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
DE69520580T 1995-09-29 1995-09-29 Hierarchische Speicheranordnung Expired - Fee Related DE69520580T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95830405A EP0768672B1 (de) 1995-09-29 1995-09-29 Hierarchische Speicheranordnung

Publications (2)

Publication Number Publication Date
DE69520580D1 true DE69520580D1 (de) 2001-05-10
DE69520580T2 DE69520580T2 (de) 2001-10-04

Family

ID=8222020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69520580T Expired - Fee Related DE69520580T2 (de) 1995-09-29 1995-09-29 Hierarchische Speicheranordnung

Country Status (3)

Country Link
US (1) US5841728A (de)
EP (1) EP0768672B1 (de)
DE (1) DE69520580T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4535563B2 (ja) * 2000-04-28 2010-09-01 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6418046B1 (en) * 2001-01-30 2002-07-09 Motorola, Inc. MRAM architecture and system

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4344005A (en) * 1978-07-18 1982-08-10 Rca Corporation Power gated decoding
US4658377A (en) * 1984-07-26 1987-04-14 Texas Instruments Incorporated Dynamic memory array with segmented bit lines
US4701885A (en) * 1984-07-26 1987-10-20 Texas Instruments Incorporated Dynamic memory array with quasi-folded bit lines
US4800525A (en) * 1984-10-31 1989-01-24 Texas Instruments Incorporated Dual ended folded bit line arrangement and addressing scheme
JPH03235290A (ja) 1990-02-09 1991-10-21 Mitsubishi Electric Corp 階層的な行選択線を有する半導体記憶装置
KR0127290B1 (ko) * 1991-11-20 1999-03-20 세끼모또 타다히로 낸드형 롬 및 그 제조 방법
JP3450467B2 (ja) * 1993-12-27 2003-09-22 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP2785717B2 (ja) * 1994-09-30 1998-08-13 日本電気株式会社 半導体記憶装置

Also Published As

Publication number Publication date
DE69520580T2 (de) 2001-10-04
US5841728A (en) 1998-11-24
EP0768672A1 (de) 1997-04-16
EP0768672B1 (de) 2001-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee