DE69519010D1 - Datenverarbeitungsgerät zur simulation von asynchronen logischen schaltkreisen - Google Patents

Datenverarbeitungsgerät zur simulation von asynchronen logischen schaltkreisen

Info

Publication number
DE69519010D1
DE69519010D1 DE69519010T DE69519010T DE69519010D1 DE 69519010 D1 DE69519010 D1 DE 69519010D1 DE 69519010 T DE69519010 T DE 69519010T DE 69519010 T DE69519010 T DE 69519010T DE 69519010 D1 DE69519010 D1 DE 69519010D1
Authority
DE
Germany
Prior art keywords
data processing
processing device
logical circuits
asynchronous logical
simulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69519010T
Other languages
English (en)
Other versions
DE69519010T2 (de
Inventor
Roy Wavish
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Koninklijke Philips NV
Original Assignee
Philips Electronics UK Ltd
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics UK Ltd, Koninklijke Philips Electronics NV filed Critical Philips Electronics UK Ltd
Application granted granted Critical
Publication of DE69519010D1 publication Critical patent/DE69519010D1/de
Publication of DE69519010T2 publication Critical patent/DE69519010T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
DE69519010T 1994-04-07 1995-03-21 Datenverarbeitungsgerät zur simulation von asynchronen logischen schaltkreisen Expired - Fee Related DE69519010T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9406931A GB9406931D0 (en) 1994-04-07 1994-04-07 Data processing apparatus
PCT/IB1995/000192 WO1995027952A2 (en) 1994-04-07 1995-03-21 Data processing apparatus

Publications (2)

Publication Number Publication Date
DE69519010D1 true DE69519010D1 (de) 2000-11-09
DE69519010T2 DE69519010T2 (de) 2001-05-10

Family

ID=10753187

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69519010T Expired - Fee Related DE69519010T2 (de) 1994-04-07 1995-03-21 Datenverarbeitungsgerät zur simulation von asynchronen logischen schaltkreisen

Country Status (6)

Country Link
US (1) US5768161A (de)
EP (1) EP0704077B1 (de)
JP (1) JPH08512160A (de)
DE (1) DE69519010T2 (de)
GB (1) GB9406931D0 (de)
WO (1) WO1995027952A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9413127D0 (en) * 1994-06-30 1994-08-24 Philips Electronics Uk Ltd Data processing apparatus
EP0824826B1 (de) * 1996-03-04 2003-10-22 Koninklijke Philips Electronics N.V. Dem benutzer zugeneigtes multimediapräsentationssystem für mehrere präsentationsartikel, welche jeder als ein agent wirken
GB9609189D0 (en) * 1996-05-02 1996-07-03 Philips Electronics Nv Adaptive process modelling and control
GB9609197D0 (en) * 1996-05-02 1996-07-03 Philips Electronics Nv Process control with evaluation of stored referential expressions
GB9616184D0 (en) * 1996-08-01 1996-09-11 Philips Electronics Nv Virtual environment navigation
GB9623336D0 (en) * 1996-11-08 1997-01-08 Philips Electronics Nv Autonomous compound agents

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4365297A (en) * 1980-12-29 1982-12-21 Forney Engineering Company Industrial control system with distributed computer implemented logic
US4845633A (en) * 1985-12-02 1989-07-04 Apple Computer Inc. System for programming graphically a programmable, asynchronous logic cell and array
GB2192471A (en) * 1986-07-10 1988-01-13 Unilever Plc Compiling control program
US5150308A (en) * 1986-09-12 1992-09-22 Digital Equipment Corporation Parameter and rule creation and modification mechanism for use by a procedure for synthesis of logic circuit designs
US5175696A (en) * 1986-09-12 1992-12-29 Digital Equipment Corporation Rule structure in a procedure for synthesis of logic circuits
US5287548A (en) * 1988-02-29 1994-02-15 Allen-Bradley Company, Inc. Programmable controller having a stored program with both machine language instructions and source code data
GB2231693A (en) * 1989-05-08 1990-11-21 Philips Electronic Associated Data processing system
JPH0341519A (ja) * 1989-07-10 1991-02-22 Hitachi Ltd 知識処理システム
US5058052A (en) * 1989-10-16 1991-10-15 Ge Fanuc Automation North America, Inc. Method for checking the syntax of an instruction list program to determine if the program is expressible as a relay ladder diagram by a programmable logic controller
US5204939A (en) * 1989-12-14 1993-04-20 Fujitsu Limited Rule base processing system and rule evaluation control method therein
DE4010571A1 (de) * 1990-04-02 1991-10-10 Siemens Ag Verfahren zum progammieren von automatisierungsvorgaengen mit einem programmiergeraet auf rechnerbasis
US5287289A (en) * 1990-04-13 1994-02-15 Hitachi, Ltd. Logic synthesis method
US5313560A (en) * 1990-05-11 1994-05-17 Hitachi, Ltd. Method for determining a supplemental transaction changing a decided transaction to satisfy a target
US5410673A (en) * 1991-09-12 1995-04-25 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for simulating a logic circuit having a plurality of interconnect logic blocks
US5392227A (en) * 1992-07-24 1995-02-21 Logic Modeling Corporation System and method for generating electronic circuit simulation models having improved accuracy
GB9220085D0 (en) * 1992-09-23 1992-11-04 Int Computers Ltd Compilation mechanism for a simulation model
US5477474A (en) * 1992-10-29 1995-12-19 Altera Corporation Computer logic simulation with dynamic modeling
US5493505A (en) * 1993-10-28 1996-02-20 Nec Usa, Inc. Initializable asynchronous circuit design
US5469367A (en) * 1994-06-06 1995-11-21 University Technologies International Inc. Methodology and apparatus for modular partitioning for the machine design of asynchronous circuits

Also Published As

Publication number Publication date
US5768161A (en) 1998-06-16
WO1995027952A3 (en) 1995-11-16
GB9406931D0 (en) 1994-06-01
DE69519010T2 (de) 2001-05-10
WO1995027952A2 (en) 1995-10-19
JPH08512160A (ja) 1996-12-17
EP0704077A2 (de) 1996-04-03
EP0704077B1 (de) 2000-10-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee