DE69517753D1 - Abholungs- und Speicherungspuffer zur nicht-sequentiellen Ausführung in einem Datenverarbeitungssystem - Google Patents

Abholungs- und Speicherungspuffer zur nicht-sequentiellen Ausführung in einem Datenverarbeitungssystem

Info

Publication number
DE69517753D1
DE69517753D1 DE69517753T DE69517753T DE69517753D1 DE 69517753 D1 DE69517753 D1 DE 69517753D1 DE 69517753 T DE69517753 T DE 69517753T DE 69517753 T DE69517753 T DE 69517753T DE 69517753 D1 DE69517753 D1 DE 69517753D1
Authority
DE
Germany
Prior art keywords
collection
data processing
processing system
sequential execution
storage buffers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69517753T
Other languages
English (en)
Inventor
Benjamin T Imai
Hung Qui Le
Dung Quoc Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69517753D1 publication Critical patent/DE69517753D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69517753T 1994-06-30 1995-04-27 Abholungs- und Speicherungspuffer zur nicht-sequentiellen Ausführung in einem Datenverarbeitungssystem Expired - Lifetime DE69517753D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/269,868 US5465336A (en) 1994-06-30 1994-06-30 Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system

Publications (1)

Publication Number Publication Date
DE69517753D1 true DE69517753D1 (de) 2000-08-10

Family

ID=23028988

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69517753T Expired - Lifetime DE69517753D1 (de) 1994-06-30 1995-04-27 Abholungs- und Speicherungspuffer zur nicht-sequentiellen Ausführung in einem Datenverarbeitungssystem

Country Status (4)

Country Link
US (1) US5465336A (de)
EP (1) EP0690371B1 (de)
JP (1) JP2986071B2 (de)
DE (1) DE69517753D1 (de)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69420540T2 (de) * 1994-01-03 2000-02-10 Intel Corp., Santa Clara Verfahren und Vorrichtung zum Implementieren eines vierstufigen Verzweigungsauflosungssystem in einem Rechnerprozessor
US5590352A (en) * 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US5627981A (en) * 1994-07-01 1997-05-06 Digital Equipment Corporation Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination
US5666494A (en) * 1995-03-31 1997-09-09 Samsung Electronics Co., Ltd. Queue management mechanism which allows entries to be processed in any order
US5848256A (en) * 1996-09-30 1998-12-08 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for address disambiguation using address component identifiers
US5978900A (en) * 1996-12-30 1999-11-02 Intel Corporation Renaming numeric and segment registers using common general register pool
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
US6014709A (en) * 1997-11-05 2000-01-11 Unisys Corporation Message flow protocol for avoiding deadlocks
US6052760A (en) * 1997-11-05 2000-04-18 Unisys Corporation Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks
US6209073B1 (en) 1998-04-27 2001-03-27 International Business Machines Corp. System and method for interlocking barrier operations in load and store queues
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6212622B1 (en) 1998-08-24 2001-04-03 Advanced Micro Devices, Inc. Mechanism for load block on store address generation
US6122727A (en) * 1998-08-24 2000-09-19 Advanced Micro Devices, Inc. Symmetrical instructions queue for high clock frequency scheduling
US6212623B1 (en) 1998-08-24 2001-04-03 Advanced Micro Devices, Inc. Universal dependency vector/queue entry
WO2000011548A1 (en) * 1998-08-24 2000-03-02 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector
US6237067B1 (en) 1998-08-31 2001-05-22 International Business Machines Corporation System and method for handling storage consistency conflict
US6223259B1 (en) 1998-10-30 2001-04-24 Telefonaktiebolaget Lm Ericsson (Publ) Reducing read cycle of memory read request for data to be partially modified by a pending write request
US6748493B1 (en) 1998-11-30 2004-06-08 International Business Machines Corporation Method and apparatus for managing memory operations in a data processing system using a store buffer
US6237066B1 (en) * 1999-03-22 2001-05-22 Sun Microsystems, Inc. Supporting multiple outstanding requests to multiple targets in a pipelined memory system
EP1050806A1 (de) 1999-05-03 2000-11-08 STMicroelectronics SA Speicheradressenvergleich
US6665761B1 (en) 1999-07-28 2003-12-16 Unisys Corporation Method and apparatus for routing interrupts in a clustered multiprocessor system
US6687818B1 (en) 1999-07-28 2004-02-03 Unisys Corporation Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system
US6481251B1 (en) * 1999-10-25 2002-11-19 Advanced Micro Devices, Inc. Store queue number assignment and tracking
US6523109B1 (en) 1999-10-25 2003-02-18 Advanced Micro Devices, Inc. Store queue multimatch detection
US6557095B1 (en) * 1999-12-27 2003-04-29 Intel Corporation Scheduling operations using a dependency matrix
US6651161B1 (en) 2000-01-03 2003-11-18 Advanced Micro Devices, Inc. Store load forward predictor untraining
US6622235B1 (en) 2000-01-03 2003-09-16 Advanced Micro Devices, Inc. Scheduler which retries load/store hit situations
US6694424B1 (en) 2000-01-03 2004-02-17 Advanced Micro Devices, Inc. Store load forward predictor training
US6564315B1 (en) 2000-01-03 2003-05-13 Advanced Micro Devices, Inc. Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
US6622237B1 (en) 2000-01-03 2003-09-16 Advanced Micro Devices, Inc. Store to load forward predictor training using delta tag
US6542984B1 (en) 2000-01-03 2003-04-01 Advanced Micro Devices, Inc. Scheduler capable of issuing and reissuing dependency chains
US7321964B2 (en) * 2003-07-08 2008-01-22 Advanced Micro Devices, Inc. Store-to-load forwarding buffer using indexed lookup
US20060129764A1 (en) * 2004-12-09 2006-06-15 International Business Machines Corporation Methods and apparatus for storing a command
US7376817B2 (en) * 2005-08-10 2008-05-20 P.A. Semi, Inc. Partial load/store forward prediction
US7634591B2 (en) * 2006-01-26 2009-12-15 International Business Machines Corporation Method and apparatus for tracking command order dependencies
US8131953B2 (en) * 2007-12-17 2012-03-06 International Business Machines Corporation Tracking store ordering hazards in an out-of-order store queue
US8112604B2 (en) 2007-12-17 2012-02-07 International Business Machines Corporation Tracking load store ordering hazards
GB2469299B (en) 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory
TWI428918B (zh) * 2009-09-29 2014-03-01 Silicon Motion Inc 記憶裝置以及記憶裝置之資料存取方法
US8418156B2 (en) * 2009-12-16 2013-04-09 Intel Corporation Two-stage commit (TSC) region for dynamic binary optimization in X86
US9128725B2 (en) 2012-05-04 2015-09-08 Apple Inc. Load-store dependency predictor content management
US9600289B2 (en) 2012-05-30 2017-03-21 Apple Inc. Load-store dependency predictor PC hashing
US9710268B2 (en) 2014-04-29 2017-07-18 Apple Inc. Reducing latency for pointer chasing loads
US9606805B1 (en) * 2015-10-19 2017-03-28 International Business Machines Corporation Accuracy of operand store compare prediction using confidence counter
US10514925B1 (en) 2016-01-28 2019-12-24 Apple Inc. Load speculation recovery
US10437595B1 (en) 2016-03-15 2019-10-08 Apple Inc. Load/store dependency predictor optimization for replayed loads
US10282109B1 (en) * 2016-09-15 2019-05-07 Altera Corporation Memory interface circuitry with distributed data reordering capabilities
US10628166B2 (en) * 2017-09-20 2020-04-21 International Business Machines Corporation Allocating and deallocating reorder queue entries for an out-of-order processor

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155666A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Instruction controlling system of vector processor
JPH063584B2 (ja) * 1983-12-19 1994-01-12 株式会社日立製作所 情報処理装置
US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
US4773041A (en) * 1986-06-02 1988-09-20 Unisys Corporation System for executing a sequence of operation codes with some codes being executed out of order in a pipeline parallel processor
JPS63131230A (ja) * 1986-11-21 1988-06-03 Hitachi Ltd 情報処理装置
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
US4992938A (en) * 1987-07-01 1991-02-12 International Business Machines Corporation Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers
US4916652A (en) * 1987-09-30 1990-04-10 International Business Machines Corporation Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures
EP0312764A3 (de) * 1987-10-19 1991-04-10 International Business Machines Corporation Datenprozessor mit mehrfachen Ausführungseinheiten zur parallelen Ausführung von mehreren Befehlsklassen
US5075840A (en) * 1989-01-13 1991-12-24 International Business Machines Corporation Tightly coupled multiprocessor instruction synchronization
US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
US5226126A (en) * 1989-02-24 1993-07-06 Nexgen Microsystems Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
US5073855A (en) * 1989-06-30 1991-12-17 Bull Hn Information Systems Inc. Resource conflict detection method and apparatus included in a pipelined processing unit
US5185871A (en) * 1989-12-26 1993-02-09 International Business Machines Corporation Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
CA2056356C (en) * 1990-03-19 1998-06-09 Haruhiko Ueno Interruption handling system
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
US5257354A (en) * 1991-01-16 1993-10-26 International Business Machines Corporation System for monitoring and undoing execution of instructions beyond a serialization point upon occurrence of in-correct results
US5261071A (en) * 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5363495A (en) * 1991-08-26 1994-11-08 International Business Machines Corporation Data processing system with multiple execution units capable of executing instructions out of sequence
EP0529303A3 (en) * 1991-08-29 1993-09-22 International Business Machines Corporation Checkpoint synchronization with instruction overlap enabled
US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device

Also Published As

Publication number Publication date
JP2986071B2 (ja) 1999-12-06
EP0690371A1 (de) 1996-01-03
US5465336A (en) 1995-11-07
EP0690371B1 (de) 2000-07-05
JPH0816395A (ja) 1996-01-19

Similar Documents

Publication Publication Date Title
DE69517753D1 (de) Abholungs- und Speicherungspuffer zur nicht-sequentiellen Ausführung in einem Datenverarbeitungssystem
DE69424944D1 (de) Datenreduktion in einem system zur analysierung von geometrischen datenbanken
DE69801418D1 (de) Datenaufteilung und -dupliziering in einem verteilten datenverarbeitungssystem
HUP0001862A3 (en) Method and system for read operations in multiprocessor computer system
DE69507290D1 (de) Gerät zur datenpuffer-überwachung in einem plattenspeichersystem
DE69530138D1 (de) System und Verfahren zur Cursorsteuerung in einem Rechner
DE69732020D1 (de) Wiedereinordnung von Speicheranforderungen in einem Datenverarbeitungssystem
DE69508923D1 (de) Datenverarbeitungssystem mit einem graphischen tablett und einem griffel und griffel zur verwendung in einem solchen system
DE69032781D1 (de) System und Verfahren zur Optimierung von Cachespeicherung in einem auf Plattenspeicher basierendem Rechnersystem
DE69433621D1 (de) Geraet zur verarbeitung von befehlen in einem rechnersystem
DE69426447D1 (de) Verfahren zur Durchführung von Bustransaktionen in einem Rechnersystem und Rechnersystem
DE3882977D1 (de) Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.
DE69833935D1 (de) Verfahren und system zur bestimmung und gebrauch von mehreren objektzuständen in einem computer-telefon integrierten system
DE68927216D1 (de) System zur verwaltung von hierarchischen informationen in einem digitalen datenverarbeitungssystem
DE69515952D1 (de) Verfahren und Vorrichtung zur Verminderung von Quartisierungsstörungen in einem hierarchischen Bildspeicher- und Wiederauffindungssystem
DE69727355D1 (de) Anordnung und Verfahren zur Taktsequenzierung in einem Datenverarbeitungssystem
DE69524306D1 (de) Informationsverarbeitungssystem und mit einem Informationsverarbeitungssystem durchgeführtes Rechnerverfahren
DE69919059D1 (de) Datenverarbeitungssytem mit einem digitalen Signalprozessor und einem Koprozessor und Datenverarbeitungsverfahren
DE69637851D1 (de) Verfahren und System für Hochleistungsmehrdrahtverarbeitung in einem Datenverarbeitungssystem
EP0753176A4 (de) Verfahren und apparat für den datenzugriff in einem digitalen rechnersystem mit mehreren prozessoren
DE69523896D1 (de) Datenverarbeitungssystem mit einer tafel und einem stift zur anwendung in einem solchen system
DE19782177T1 (de) Verfahren und Einrichtung zur Durchführung von TLB-Shootdown-Operationen in einem Multiprozessorsystem
EP0465321A3 (en) Ensuring data integrity in multiprocessor or pipelined processor system
DE69127025D1 (de) Fehlererkennung und -beseitigung in einem Datenverarbeitungssystem
DE69825687D1 (de) System und Verfahren zur Umwandlung von Prozessortaktwerten in einem Mehrprozessorsystem

Legal Events

Date Code Title Description
8332 No legal effect for de