DE69514774D1 - Faltungsstufe für faltungsanalog/digitalwandler - Google Patents

Faltungsstufe für faltungsanalog/digitalwandler

Info

Publication number
DE69514774D1
DE69514774D1 DE69514774T DE69514774T DE69514774D1 DE 69514774 D1 DE69514774 D1 DE 69514774D1 DE 69514774 T DE69514774 T DE 69514774T DE 69514774 T DE69514774 T DE 69514774T DE 69514774 D1 DE69514774 D1 DE 69514774D1
Authority
DE
Germany
Prior art keywords
folding
digital converter
analog
level
folding level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69514774T
Other languages
English (en)
Other versions
DE69514774T2 (de
Inventor
Gerardus Venes
Bram Nauta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Application granted granted Critical
Publication of DE69514774D1 publication Critical patent/DE69514774D1/de
Publication of DE69514774T2 publication Critical patent/DE69514774T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/20Increasing resolution using an n bit system to obtain n + m bits
    • H03M1/202Increasing resolution using an n bit system to obtain n + m bits by interpolation
    • H03M1/203Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit
    • H03M1/204Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators
    • H03M1/205Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators using resistor strings for redistribution of the original reference signals or signals derived therefrom
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12Analogue/digital converters
    • H03M1/14Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/141Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit in which at least one step is of the folding type; Folding stages therefore
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607Offset or drift compensation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
DE69514774T 1994-07-07 1995-06-27 Faltungsstufe für faltungsanalog/digitalwandler Expired - Fee Related DE69514774T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP94201958 1994-07-07
PCT/IB1995/000519 WO1996002087A1 (en) 1994-07-07 1995-06-27 Folding stage for a folding analog-to-digital converter

Publications (2)

Publication Number Publication Date
DE69514774D1 true DE69514774D1 (de) 2000-03-02
DE69514774T2 DE69514774T2 (de) 2000-07-27

Family

ID=8217018

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69514774T Expired - Fee Related DE69514774T2 (de) 1994-07-07 1995-06-27 Faltungsstufe für faltungsanalog/digitalwandler

Country Status (6)

Country Link
US (1) US5633638A (de)
EP (1) EP0722632B1 (de)
JP (1) JP3555955B2 (de)
KR (1) KR960705410A (de)
DE (1) DE69514774T2 (de)
WO (1) WO1996002087A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970705872A (ko) * 1995-07-11 1997-10-09 요트. 게. 아. 롤페즈 디지탈 N-비트 그레이 코드를 발생하는 아날로그 대 디지탈 컨버터(Analog-to-digital converter for generating a digital N-bit gray-code)
CN1169217A (zh) * 1995-09-08 1997-12-31 菲利浦电子有限公司 具有折叠和内插的模/数变换
SG68676A1 (en) * 1997-08-15 1999-11-16 Texas Instruments Inc Current comparator and method therefor
SG71140A1 (en) 1997-08-15 2000-03-21 Texas Instruments Inc Differential pair-based folding interpolator circuit for an analog-to-digital converter
US6339391B1 (en) * 1999-12-13 2002-01-15 Lsi Logic Corporation Method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like
KR100416969B1 (ko) * 2001-12-07 2004-02-05 삼성전자주식회사 프로그램 가능한 인터폴레이터를 사용하는아날로그/디지탈 변환장치 및 방법
US7009547B2 (en) * 2001-12-17 2006-03-07 University Of Utah Research Foundation Current steering folding circuit
US7839317B1 (en) 2009-07-13 2010-11-23 Don Roy Sauer Folding comparator compatible with level-crossing sampling
FR3006832A1 (fr) * 2013-06-07 2014-12-12 St Microelectronics Sa Circuit et procede de correction de decalage temporel

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386339A (en) * 1980-03-31 1983-05-31 Hewlett-Packard Company Direct flash analog-to-digital converter and method
US5126742A (en) * 1990-11-06 1992-06-30 Signal Processing Technologies, Inc. Analog to digital converter with double folding interpolation circuitry
US5070332A (en) * 1991-03-18 1991-12-03 Burr-Brown Corporation Two-step subranging analog to digital converter
US5307067A (en) * 1992-04-20 1994-04-26 Matsushita Electric Industrial Co., Ltd. Folding circuit and analog-to-digital converter
US5376937A (en) * 1993-02-22 1994-12-27 The Regents Of The University Of California Folding circuit

Also Published As

Publication number Publication date
EP0722632B1 (de) 2000-01-26
JPH09503364A (ja) 1997-03-31
WO1996002087A1 (en) 1996-01-25
DE69514774T2 (de) 2000-07-27
EP0722632A1 (de) 1996-07-24
JP3555955B2 (ja) 2004-08-18
KR960705410A (ko) 1996-10-09
US5633638A (en) 1997-05-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee