DE69510966D1 - Verfahren zur Lenkung von Instruktionen in einem Rechnersystem und Rechnersystem zur Durchführung dieses Verfahrens - Google Patents

Verfahren zur Lenkung von Instruktionen in einem Rechnersystem und Rechnersystem zur Durchführung dieses Verfahrens

Info

Publication number
DE69510966D1
DE69510966D1 DE69510966T DE69510966T DE69510966D1 DE 69510966 D1 DE69510966 D1 DE 69510966D1 DE 69510966 T DE69510966 T DE 69510966T DE 69510966 T DE69510966 T DE 69510966T DE 69510966 D1 DE69510966 D1 DE 69510966D1
Authority
DE
Germany
Prior art keywords
computer system
instructions
carrying
control
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69510966T
Other languages
English (en)
Other versions
DE69510966T2 (de
Inventor
Nazeemudeen Noordeen
Jason Zheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69510966D1 publication Critical patent/DE69510966D1/de
Application granted granted Critical
Publication of DE69510966T2 publication Critical patent/DE69510966T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69510966T 1994-02-14 1995-02-03 Verfahren zur Lenkung von Instruktionen in einem Rechnersystem und Rechnersystem zur Durchführung dieses Verfahrens Expired - Lifetime DE69510966T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/194,899 US5974534A (en) 1994-02-14 1994-02-14 Predecoding and steering mechanism for instructions in a superscalar processor

Publications (2)

Publication Number Publication Date
DE69510966D1 true DE69510966D1 (de) 1999-09-02
DE69510966T2 DE69510966T2 (de) 1999-12-09

Family

ID=22719320

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69510966T Expired - Lifetime DE69510966T2 (de) 1994-02-14 1995-02-03 Verfahren zur Lenkung von Instruktionen in einem Rechnersystem und Rechnersystem zur Durchführung dieses Verfahrens

Country Status (4)

Country Link
US (1) US5974534A (de)
EP (1) EP0667571B1 (de)
JP (1) JP3670043B2 (de)
DE (1) DE69510966T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5829031A (en) * 1996-02-23 1998-10-27 Advanced Micro Devices, Inc. Microprocessor configured to detect a group of instructions and to perform a specific function upon detection
JPH10232779A (ja) * 1997-01-24 1998-09-02 Texas Instr Inc <Ti> 命令並列処理方法及び装置
GB2332075B (en) * 1997-12-06 2002-08-07 Mitel Corp Optimized instruction storage and distribution for parallel processors architectures
EP1050810A1 (de) 1999-05-03 2000-11-08 STMicroelectronics SA Rechnersystem mit mehreren funktionellen Einheiten
EP1102165A1 (de) * 1999-11-15 2001-05-23 Texas Instruments Incorporated Mikroprozessor mit Ausführungspaket über zwei oder mehr Abholpakete verbreitet
US7039790B1 (en) 1999-11-15 2006-05-02 Texas Instruments Incorporated Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit
EP1367485B1 (de) * 2002-05-31 2012-10-31 STMicroelectronics Limited Pipeline-Verarbeitung
AT500858B8 (de) * 2004-08-17 2007-02-15 Martin Schoeberl Instruction cache für echtzeitsysteme
US9201801B2 (en) * 2010-09-15 2015-12-01 International Business Machines Corporation Computing device with asynchronous auxiliary execution unit
CN102495726B (zh) 2011-11-15 2015-05-20 无锡德思普科技有限公司 机会多线程方法及处理器
CN103187955B (zh) * 2011-12-31 2016-08-03 意法半导体研发（上海）有限公司 共栅共源驱动电路
US9766895B2 (en) * 2014-02-06 2017-09-19 Optimum Semiconductor Technologies, Inc. Opportunity multithreading in a multithreaded processor with instruction chaining capability
US9558000B2 (en) * 2014-02-06 2017-01-31 Optimum Semiconductor Technologies, Inc. Multithreading using an ordered list of hardware contexts

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
KR940003383B1 (ko) * 1989-08-28 1994-04-21 니뽄 덴끼 가부시끼가이샤 파이프라인 처리 방식으로 동작하는 프리디코더 유니트 및 주 디코더 유니트를 구비한 마이크로프로세서
JP2818249B2 (ja) * 1990-03-30 1998-10-30 株式会社東芝 電子計算機
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
EP0459232B1 (de) * 1990-05-29 1998-12-09 National Semiconductor Corporation Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
JPH0476626A (ja) * 1990-07-13 1992-03-11 Toshiba Corp マイクロコンピュータ
US5337415A (en) * 1992-12-04 1994-08-09 Hewlett-Packard Company Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency

Also Published As

Publication number Publication date
US5974534A (en) 1999-10-26
JPH07253887A (ja) 1995-10-03
EP0667571A3 (de) 1995-12-13
EP0667571A2 (de) 1995-08-16
JP3670043B2 (ja) 2005-07-13
EP0667571B1 (de) 1999-07-28
DE69510966T2 (de) 1999-12-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE