DE69430080T2 - Abschaltschaltung von Randübergangsabfühlung zur Änderung von Betriebsmodi einer Speicheranordnung - Google Patents

Abschaltschaltung von Randübergangsabfühlung zur Änderung von Betriebsmodi einer Speicheranordnung

Info

Publication number
DE69430080T2
DE69430080T2 DE69430080T DE69430080T DE69430080T2 DE 69430080 T2 DE69430080 T2 DE 69430080T2 DE 69430080 T DE69430080 T DE 69430080T DE 69430080 T DE69430080 T DE 69430080T DE 69430080 T2 DE69430080 T2 DE 69430080T2
Authority
DE
Germany
Prior art keywords
switch
operating modes
memory arrangement
edge transition
changing operating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430080T
Other languages
English (en)
Other versions
DE69430080D1 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE69430080D1 publication Critical patent/DE69430080D1/de
Publication of DE69430080T2 publication Critical patent/DE69430080T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69430080T 1993-09-30 1994-09-28 Abschaltschaltung von Randübergangsabfühlung zur Änderung von Betriebsmodi einer Speicheranordnung Expired - Fee Related DE69430080T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/129,763 US5418756A (en) 1993-09-30 1993-09-30 Edge transition detection disable circuit to alter memory device operating characteristics

Publications (2)

Publication Number Publication Date
DE69430080D1 DE69430080D1 (de) 2002-04-11
DE69430080T2 true DE69430080T2 (de) 2002-09-05

Family

ID=22441484

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69424735T Expired - Fee Related DE69424735T2 (de) 1993-09-30 1994-09-28 Schaltung zum Abschalten eines Flankendetektors zum Ändern der Betriebscharakteristiken eines Speichers
DE69430080T Expired - Fee Related DE69430080T2 (de) 1993-09-30 1994-09-28 Abschaltschaltung von Randübergangsabfühlung zur Änderung von Betriebsmodi einer Speicheranordnung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69424735T Expired - Fee Related DE69424735T2 (de) 1993-09-30 1994-09-28 Schaltung zum Abschalten eines Flankendetektors zum Ändern der Betriebscharakteristiken eines Speichers

Country Status (4)

Country Link
US (1) US5418756A (de)
EP (2) EP0952549B1 (de)
JP (1) JPH07169272A (de)
DE (2) DE69424735T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69413478T2 (de) * 1993-07-30 1999-02-11 Sgs Thomson Microelectronics Inverter mit Verzögerungselement mit variabler Impedanz
US5602795A (en) * 1994-01-12 1997-02-11 Sun Microsystems, Inc. Method and apparatus for implementing a high-speed dynamic line driver
US5469473A (en) * 1994-04-15 1995-11-21 Texas Instruments Incorporated Transceiver circuit with transition detection
US5778428A (en) * 1995-12-22 1998-07-07 International Business Machines Corporation Programmable high performance mode for multi-way associative cache/memory designs
US6388931B1 (en) 1999-02-25 2002-05-14 Micron Technology, Inc. Dummy wordline for controlling the timing of the firing of sense amplifiers in a memory device in relation to the firing of wordlines in the memory device
US7328428B2 (en) * 2003-09-23 2008-02-05 Trivergent Technologies, Inc. System and method for generating data validation rules
TW200520388A (en) * 2003-10-10 2005-06-16 Atmel Corp Selectable delay pulse generator
US7346710B2 (en) 2004-04-12 2008-03-18 Stephen Waller Melvin Apparatus for input/output expansion without additional control line wherein first and second signals transition directly to a different state when necessary to perform input/output
JP2008021340A (ja) * 2006-07-10 2008-01-31 Toshiba Microelectronics Corp 半導体装置
US7782093B2 (en) 2007-05-23 2010-08-24 Infineon Technologies Ag Integrated circuit and method of detecting a signal edge transition

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61196498A (ja) * 1985-02-26 1986-08-30 Mitsubishi Electric Corp 半導体記憶装置
JPS634492A (ja) * 1986-06-23 1988-01-09 Mitsubishi Electric Corp 半導体記憶装置
JPS63263689A (ja) * 1987-04-20 1988-10-31 Mitsubishi Electric Corp 半導体記憶装置
KR900008554B1 (ko) * 1988-04-23 1990-11-24 삼성전자 주식회사 메모리 동작모드 선택회로
US4987325A (en) * 1988-07-13 1991-01-22 Samsung Electronics Co., Ltd. Mode selecting circuit for semiconductor memory device
US5214610A (en) * 1989-09-22 1993-05-25 Texas Instruments Incorporated Memory with selective address transition detection for cache operation
EP0419852A3 (en) * 1989-09-22 1992-08-05 Texas Instruments Incorporated A memory with selective address transition detection for cache operation
JP2991479B2 (ja) * 1990-11-16 1999-12-20 富士通株式会社 半導体集積回路及び半導体記憶装置

Also Published As

Publication number Publication date
EP0646926A3 (de) 1995-11-15
EP0952549A2 (de) 1999-10-27
DE69424735T2 (de) 2000-11-30
JPH07169272A (ja) 1995-07-04
EP0646926A2 (de) 1995-04-05
DE69424735D1 (de) 2000-07-06
US5418756A (en) 1995-05-23
EP0952549A3 (de) 2000-07-05
DE69430080D1 (de) 2002-04-11
EP0952549B1 (de) 2002-03-06
EP0646926B1 (de) 2000-05-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee