DE69421591T2 - Dynamischer Bus von hoher Dichte - Google Patents

Dynamischer Bus von hoher Dichte

Info

Publication number
DE69421591T2
DE69421591T2 DE69421591T DE69421591T DE69421591T2 DE 69421591 T2 DE69421591 T2 DE 69421591T2 DE 69421591 T DE69421591 T DE 69421591T DE 69421591 T DE69421591 T DE 69421591T DE 69421591 T2 DE69421591 T2 DE 69421591T2
Authority
DE
Germany
Prior art keywords
dynamic high
density bus
bus
density
dynamic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69421591T
Other languages
English (en)
Other versions
DE69421591D1 (de
Inventor
Teik-Chung Tan
Stephen C Kromer
Joe Peters
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69421591D1 publication Critical patent/DE69421591D1/de
Application granted granted Critical
Publication of DE69421591T2 publication Critical patent/DE69421591T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Quality & Reliability (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
DE69421591T 1993-10-21 1994-09-07 Dynamischer Bus von hoher Dichte Expired - Lifetime DE69421591T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14067193A 1993-10-21 1993-10-21

Publications (2)

Publication Number Publication Date
DE69421591D1 DE69421591D1 (de) 1999-12-16
DE69421591T2 true DE69421591T2 (de) 2000-06-08

Family

ID=22492295

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421591T Expired - Lifetime DE69421591T2 (de) 1993-10-21 1994-09-07 Dynamischer Bus von hoher Dichte

Country Status (4)

Country Link
US (1) US5815031A (de)
EP (1) EP0650194B1 (de)
JP (1) JP3774243B2 (de)
DE (1) DE69421591T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008705A (en) * 1998-02-26 1999-12-28 International Business Machines Corporation Crosstalk suppression in wide, high-speed buses
EP0977263A3 (de) * 1998-07-31 2002-07-10 STMicroelectronics, Inc. Anordnung und Verfahren zur Reduzierung der Laufzeit in einem Leiter
US6985004B2 (en) 2001-02-12 2006-01-10 International Business Machines Corporation Wiring optimizations for power
US20030117183A1 (en) * 2001-12-20 2003-06-26 Claude Thibeault Methods, apparatus, and systems for reducing interference on nearby conductors
US7609778B2 (en) * 2001-12-20 2009-10-27 Richard S. Norman Methods, apparatus, and systems for reducing interference on nearby conductors
US6703868B2 (en) 2001-12-20 2004-03-09 Hyperchip Inc. Methods, apparatus, and systems for reducing interference on nearby conductors
US6897497B2 (en) * 2001-12-20 2005-05-24 Hyperchip Inc. Methods, apparatus, and systems for reducing interference on nearby conductors
JP4345428B2 (ja) 2003-10-10 2009-10-14 エルピーダメモリ株式会社 信号線駆動方法、回路、および半導体メモリ装置
FR3051266B1 (fr) * 2016-05-12 2019-07-05 Fogale Nanotech Dispositif d'interface capacitive a structure d'electrodes mixtes, et appareil comprenant le dispositif

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048922B1 (de) * 1980-09-26 1986-04-23 Kabushiki Kaisha Toshiba Dynamische Signalerzeugungsschaltung
JPS6260255A (ja) * 1985-09-09 1987-03-16 Nec Corp 半導体記憶装置
DE3641452C1 (de) * 1986-12-04 1988-07-07 Nixdorf Computer Ag In integrierter Technik hergestellter Baustein zur Erstellung integrierter Schaltungen
JPS63238713A (ja) * 1987-03-26 1988-10-04 Oki Electric Ind Co Ltd 遅延回路
JPH0828421B2 (ja) * 1987-08-27 1996-03-21 株式会社東芝 半導体集積回路装置
JPH0265240A (ja) * 1988-08-31 1990-03-05 Seiko Epson Corp 半導体集積装置
US5073729A (en) * 1990-06-22 1991-12-17 Actel Corporation Segmented routing architecture
US5208764A (en) * 1990-10-29 1993-05-04 Sun Microsystems, Inc. Method for optimizing automatic place and route layout for full scan circuits
US5175515A (en) * 1991-06-21 1992-12-29 Compaq Computer Corporation Signal routing technique for electronic systems
JP3179800B2 (ja) * 1991-07-22 2001-06-25 株式会社日立製作所 半導体集積回路装置
KR940008132B1 (ko) * 1991-11-28 1994-09-03 삼성전자 주식회사 신호선간의 잡음을 억제하는 메모리 소자
JPH05233220A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd 演算回路
US5306967A (en) * 1992-05-29 1994-04-26 Integrated Device Technology, Inc. Apparatus for improving signal transmission along parallel lines

Also Published As

Publication number Publication date
DE69421591D1 (de) 1999-12-16
EP0650194A1 (de) 1995-04-26
US5815031A (en) 1998-09-29
EP0650194B1 (de) 1999-11-10
JP3774243B2 (ja) 2006-05-10
JPH07169843A (ja) 1995-07-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HOESSLE PATENTANWAELTE PARTNERSCHAFT, 70173 STUTTG

8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY