DE69420931D1 - Zu wiederholten Multiplikationen ohne die Benutzung eines externen Bus fähiger Multiplizierer mit einem Layout - Google Patents
Zu wiederholten Multiplikationen ohne die Benutzung eines externen Bus fähiger Multiplizierer mit einem LayoutInfo
- Publication number
- DE69420931D1 DE69420931D1 DE69420931T DE69420931T DE69420931D1 DE 69420931 D1 DE69420931 D1 DE 69420931D1 DE 69420931 T DE69420931 T DE 69420931T DE 69420931 T DE69420931 T DE 69420931T DE 69420931 D1 DE69420931 D1 DE 69420931D1
- Authority
- DE
- Germany
- Prior art keywords
- multiplier
- layout
- external bus
- repeated multiplications
- multiplications
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5290339A JP2600591B2 (ja) | 1993-11-19 | 1993-11-19 | 乗算器 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69420931D1 true DE69420931D1 (de) | 1999-11-04 |
DE69420931T2 DE69420931T2 (de) | 2000-05-18 |
Family
ID=17754782
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69420931T Expired - Fee Related DE69420931T2 (de) | 1993-11-19 | 1994-11-11 | Zu wiederholten Multiplikationen ohne die Benutzung eines externen Bus fähiger Multiplizierer mit einem Layout |
Country Status (4)
Country | Link |
---|---|
US (1) | US5544084A (de) |
EP (1) | EP0654731B1 (de) |
JP (1) | JP2600591B2 (de) |
DE (1) | DE69420931T2 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5870322A (en) * | 1995-05-22 | 1999-02-09 | Samsung Electronics Co., Ltd. | Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication |
US5790446A (en) * | 1995-07-05 | 1998-08-04 | Sun Microsystems, Inc. | Floating point multiplier with reduced critical paths using delay matching techniques |
JP3532338B2 (ja) * | 1996-02-27 | 2004-05-31 | 株式会社ルネサステクノロジ | 乗算装置 |
US20110264719A1 (en) * | 2008-10-30 | 2011-10-27 | Audioasics A/S | High radix digital multiplier |
KR102143562B1 (ko) * | 2018-12-14 | 2020-08-12 | 단국대학교 산학협력단 | Ab 곱셈 및 ab^2 곱셈의 멀티 연산 장치 및 방법 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55105732A (en) * | 1979-02-08 | 1980-08-13 | Nippon Telegr & Teleph Corp <Ntt> | Multiplier |
US4646257A (en) * | 1983-10-03 | 1987-02-24 | Texas Instruments Incorporated | Digital multiplication circuit for use in a microprocessor |
KR940002479B1 (ko) * | 1990-03-20 | 1994-03-24 | 후지쓰 가부시끼가이샤 | 고속 디지탈 병렬승산기(multiplier) |
JPH04316129A (ja) * | 1991-04-16 | 1992-11-06 | Matsushita Electric Ind Co Ltd | 乗算器 |
US5291431A (en) * | 1991-06-03 | 1994-03-01 | General Electric Company | Array multiplier adapted for tiled layout by silicon compiler |
-
1993
- 1993-11-19 JP JP5290339A patent/JP2600591B2/ja not_active Expired - Fee Related
-
1994
- 1994-11-07 US US08/335,964 patent/US5544084A/en not_active Expired - Lifetime
- 1994-11-11 DE DE69420931T patent/DE69420931T2/de not_active Expired - Fee Related
- 1994-11-11 EP EP94117851A patent/EP0654731B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2600591B2 (ja) | 1997-04-16 |
EP0654731B1 (de) | 1999-09-29 |
EP0654731A1 (de) | 1995-05-24 |
JPH07141150A (ja) | 1995-06-02 |
DE69420931T2 (de) | 2000-05-18 |
US5544084A (en) | 1996-08-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |