DE69420841T2 - Verfahren zur Eliminierung des Antenneneffekts während der Fabrikation - Google Patents

Verfahren zur Eliminierung des Antenneneffekts während der Fabrikation

Info

Publication number
DE69420841T2
DE69420841T2 DE69420841T DE69420841T DE69420841T2 DE 69420841 T2 DE69420841 T2 DE 69420841T2 DE 69420841 T DE69420841 T DE 69420841T DE 69420841 T DE69420841 T DE 69420841T DE 69420841 T2 DE69420841 T2 DE 69420841T2
Authority
DE
Germany
Prior art keywords
eliminating
effect during
during manufacturing
antenna effect
antenna
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69420841T
Other languages
English (en)
Other versions
DE69420841D1 (de
Inventor
Bill Hsu
Joe Ko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Application granted granted Critical
Publication of DE69420841D1 publication Critical patent/DE69420841D1/de
Publication of DE69420841T2 publication Critical patent/DE69420841T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE69420841T 1994-07-13 1994-07-13 Verfahren zur Eliminierung des Antenneneffekts während der Fabrikation Expired - Lifetime DE69420841T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94305122A EP0693783B1 (de) 1994-07-13 1994-07-13 Verfahren zur Eliminierung des Antenneneffekts während der Fabrikation

Publications (2)

Publication Number Publication Date
DE69420841D1 DE69420841D1 (de) 1999-10-28
DE69420841T2 true DE69420841T2 (de) 2000-01-05

Family

ID=8217768

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69420841T Expired - Lifetime DE69420841T2 (de) 1994-07-13 1994-07-13 Verfahren zur Eliminierung des Antenneneffekts während der Fabrikation

Country Status (2)

Country Link
EP (1) EP0693783B1 (de)
DE (1) DE69420841T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2766013B1 (fr) * 1997-07-10 1999-09-10 Sgs Thomson Microelectronics Piste d'interconnexion reliant, sur plusieurs niveaux de metallisation, une grille isolee d'un transistor a une diode de decharge au sein d'un circuit integre, et procede de realisation d'une telle piste

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1215268B (it) * 1985-04-26 1990-01-31 Ates Componenti Elettron Apparecchio e metodo per il confezionamento perfezionato di dispositivi semiconduttori.
US4941028A (en) * 1988-08-10 1990-07-10 Actel Corporation Structure for protecting thin dielectrics during processing
JPH06105709B2 (ja) * 1989-12-02 1994-12-21 東芝マイクロエレクトロニクス株式会社 半導体集積回路装置
JP2616227B2 (ja) * 1990-11-24 1997-06-04 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
EP0693783A1 (de) 1996-01-24
EP0693783B1 (de) 1999-09-22
DE69420841D1 (de) 1999-10-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition