DE69419589T2 - Verfahren zum prüfgerechten Entwurf von CMOS und BICMOS IC's - Google Patents

Verfahren zum prüfgerechten Entwurf von CMOS und BICMOS IC's

Info

Publication number
DE69419589T2
DE69419589T2 DE69419589T DE69419589T DE69419589T2 DE 69419589 T2 DE69419589 T2 DE 69419589T2 DE 69419589 T DE69419589 T DE 69419589T DE 69419589 T DE69419589 T DE 69419589T DE 69419589 T2 DE69419589 T2 DE 69419589T2
Authority
DE
Germany
Prior art keywords
bicmos
cmos
procedure
test
compliant design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69419589T
Other languages
English (en)
Other versions
DE69419589D1 (de
Inventor
Luigi Penza Luigi Penza
Michele Favalli Michel Favalli
Bruno Ricco' Bruno Ricco'
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69419589D1 publication Critical patent/DE69419589D1/de
Application granted granted Critical
Publication of DE69419589T2 publication Critical patent/DE69419589T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G01R31/3008—Quiescent current [IDDQ] test or leakage current test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G01R31/3012—Built-In-Current test [BIC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE69419589T 1994-01-24 1994-01-24 Verfahren zum prüfgerechten Entwurf von CMOS und BICMOS IC's Expired - Fee Related DE69419589T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830023A EP0664512B1 (de) 1994-01-24 1994-01-24 Verfahren zum prüfgerechten Entwurf von CMOS und BICMOS IC's

Publications (2)

Publication Number Publication Date
DE69419589D1 DE69419589D1 (de) 1999-08-26
DE69419589T2 true DE69419589T2 (de) 1999-11-11

Family

ID=8218366

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419589T Expired - Fee Related DE69419589T2 (de) 1994-01-24 1994-01-24 Verfahren zum prüfgerechten Entwurf von CMOS und BICMOS IC's

Country Status (4)

Country Link
US (1) US5581563A (de)
EP (1) EP0664512B1 (de)
JP (1) JPH07218578A (de)
DE (1) DE69419589T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3429082B2 (ja) * 1994-09-30 2003-07-22 株式会社リコー テストベクタ編集装置
US6252417B1 (en) 1999-04-22 2001-06-26 International Business Machines Corporation Fault identification by voltage potential signature
CA2364421A1 (en) * 2001-12-05 2003-06-05 Ecole De Technologie Superieure Integrated circuit testing system and method
US6949935B1 (en) * 2002-11-01 2005-09-27 Cypress Semiconductor Corp. Method and system for built in testing of switch functionality of tunable capacitor arrays
US6930500B2 (en) * 2003-08-01 2005-08-16 Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College IDDQ testing of CMOS mixed-signal integrated circuits
US7352170B2 (en) * 2006-06-13 2008-04-01 International Business Machines Corporation Exhaustive diagnosis of bridging defects in an integrated circuit including multiple nodes using test vectors and IDDQ measurements
EP2093580B1 (de) * 2008-02-25 2012-08-15 Dialog Semiconductor GmbH Versorgungsstrombasierte Prüfung von CMOS-Ausgangsstufen

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025344A (en) * 1988-11-30 1991-06-18 Carnegie Mellon University Built-in current testing of integrated circuits
US5390193A (en) * 1992-10-28 1995-02-14 Motorola, Inc. Test pattern generation

Also Published As

Publication number Publication date
DE69419589D1 (de) 1999-08-26
EP0664512A1 (de) 1995-07-26
EP0664512B1 (de) 1999-07-21
US5581563A (en) 1996-12-03
JPH07218578A (ja) 1995-08-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee