DE69419269D1 - Verfahren zur automatischen Ermittlung von offenen Schaltkreisen - Google Patents

Verfahren zur automatischen Ermittlung von offenen Schaltkreisen

Info

Publication number
DE69419269D1
DE69419269D1 DE69419269T DE69419269T DE69419269D1 DE 69419269 D1 DE69419269 D1 DE 69419269D1 DE 69419269 T DE69419269 T DE 69419269T DE 69419269 T DE69419269 T DE 69419269T DE 69419269 D1 DE69419269 D1 DE 69419269D1
Authority
DE
Germany
Prior art keywords
circuit
input pin
fault
procedure
occurred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69419269T
Other languages
English (en)
Other versions
DE69419269T2 (de
Inventor
Gordon D Robinson
Michael W Hamblin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Genrad Inc
Original Assignee
Genrad Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genrad Inc filed Critical Genrad Inc
Publication of DE69419269D1 publication Critical patent/DE69419269D1/de
Application granted granted Critical
Publication of DE69419269T2 publication Critical patent/DE69419269T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2812—Checking for open circuits or shorts, e.g. solder bridges; Testing conductivity, resistivity or impedance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
DE69419269T 1993-02-05 1994-01-12 Verfahren zur automatischen Ermittlung von offenen Schaltkreisen Expired - Lifetime DE69419269T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/014,154 US5414715A (en) 1993-02-05 1993-02-05 Method for automatic open-circuit detection

Publications (2)

Publication Number Publication Date
DE69419269D1 true DE69419269D1 (de) 1999-08-05
DE69419269T2 DE69419269T2 (de) 1999-12-09

Family

ID=21763842

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69419269T Expired - Lifetime DE69419269T2 (de) 1993-02-05 1994-01-12 Verfahren zur automatischen Ermittlung von offenen Schaltkreisen

Country Status (4)

Country Link
US (1) US5414715A (de)
EP (1) EP0611036B1 (de)
JP (1) JP2680259B2 (de)
DE (1) DE69419269T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5617430A (en) * 1993-12-22 1997-04-01 International Business Machines Corporation Testing system interconnections using dynamic configuration and test generation
KR970011651B1 (ko) * 1994-02-02 1997-07-12 삼성전자 주식회사 반도체 소자의 버스라인 블록화에 의한 단선 검사장치 및 검사방법
US6202181B1 (en) * 1996-11-04 2001-03-13 The Regents Of The University Of California Method for diagnosing bridging faults in integrated circuits
US6536008B1 (en) * 1998-10-27 2003-03-18 Logic Vision, Inc. Fault insertion method, boundary scan cells, and integrated circuit for use therewith
US6708306B2 (en) * 2000-12-18 2004-03-16 Cadence Design Systems, Inc. Method for diagnosing failures using invariant analysis
US7092848B2 (en) * 2003-12-22 2006-08-15 Caterpillar Inc. Control system health test system and method
US7137083B2 (en) * 2004-04-01 2006-11-14 Verigy Ipco Verification of integrated circuit tests using test simulation and integrated circuit simulation with simulated failure
GB0804654D0 (en) * 2008-03-13 2008-04-16 Smith & Nephew Vacuum closure device
JP5573638B2 (ja) * 2010-12-06 2014-08-20 日本電気株式会社 情報処理装置及びその作動方法
US9641070B2 (en) 2014-06-11 2017-05-02 Allegro Microsystems, Llc Circuits and techniques for detecting an open pin condition of an integrated circuit
US9934341B2 (en) * 2015-11-11 2018-04-03 International Business Machines Corporation Simulation of modifications to microprocessor design
WO2019240806A1 (en) * 2018-06-14 2019-12-19 Hewlett-Packard Development Company, L.P. Conferencing with error state hid notification
US12007423B2 (en) * 2021-09-02 2024-06-11 Qmax Test Equipments Pvt, Ltd Portable nodal impedance analyser

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791359A (en) * 1987-11-18 1988-12-13 Zehntel, Inc. Method of detecting possibly electrically-open connections between circuit nodes and pins connected to those nodes
US4937826A (en) * 1988-09-09 1990-06-26 Crosscheck Technology, Inc. Method and apparatus for sensing defects in integrated circuit elements
JPH0299877A (ja) * 1988-10-07 1990-04-11 Hitachi Ltd 集積回路部品及びその接続検査方法
US5058112A (en) * 1989-07-31 1991-10-15 Ag Communication Systems Corporation Programmable fault insertion circuit
US5321701A (en) * 1990-12-06 1994-06-14 Teradyne, Inc. Method and apparatus for a minimal memory in-circuit digital tester

Also Published As

Publication number Publication date
JP2680259B2 (ja) 1997-11-19
EP0611036B1 (de) 1999-06-30
DE69419269T2 (de) 1999-12-09
EP0611036A1 (de) 1994-08-17
JPH06289102A (ja) 1994-10-18
US5414715A (en) 1995-05-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition