DE69407529D1 - Vorrichtung zur Überwachung der Phasenverschiebung zwischen zwei Taktsignalen - Google Patents

Vorrichtung zur Überwachung der Phasenverschiebung zwischen zwei Taktsignalen

Info

Publication number
DE69407529D1
DE69407529D1 DE69407529T DE69407529T DE69407529D1 DE 69407529 D1 DE69407529 D1 DE 69407529D1 DE 69407529 T DE69407529 T DE 69407529T DE 69407529 T DE69407529 T DE 69407529T DE 69407529 D1 DE69407529 D1 DE 69407529D1
Authority
DE
Germany
Prior art keywords
clock signals
monitoring
phase shift
flops
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69407529T
Other languages
English (en)
Other versions
DE69407529T2 (de
Inventor
Jean-Pierre Schoellkopf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69407529D1 publication Critical patent/DE69407529D1/de
Publication of DE69407529T2 publication Critical patent/DE69407529T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/26—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being duration, interval, position, frequency, or sequence
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measuring Phase Differences (AREA)
DE69407529T 1993-10-11 1994-10-10 Vorrichtung zur Überwachung der Phasenverschiebung zwischen zwei Taktsignalen Expired - Fee Related DE69407529T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9312451A FR2711286B1 (fr) 1993-10-11 1993-10-11 Dispositif de surveillance du déphasage entre deux signaux d'horloge.

Publications (2)

Publication Number Publication Date
DE69407529D1 true DE69407529D1 (de) 1998-02-05
DE69407529T2 DE69407529T2 (de) 1998-06-04

Family

ID=9451993

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69407529T Expired - Fee Related DE69407529T2 (de) 1993-10-11 1994-10-10 Vorrichtung zur Überwachung der Phasenverschiebung zwischen zwei Taktsignalen

Country Status (5)

Country Link
US (1) US5498983A (de)
EP (1) EP0648017B1 (de)
JP (1) JP2657363B2 (de)
DE (1) DE69407529T2 (de)
FR (1) FR2711286B1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2760284B2 (ja) * 1994-06-27 1998-05-28 日本電気株式会社 半導体集積回路装置
WO1997002493A2 (en) * 1995-07-06 1997-01-23 Philips Electronics N.V. A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing
US5754063A (en) * 1996-06-27 1998-05-19 Intel Corporation Method and apparatus to measure internal node timing
JPH11272353A (ja) * 1998-03-19 1999-10-08 Toshiba Corp クロック供給回路及びデータ転送回路
JP2000009809A (ja) * 1998-06-26 2000-01-14 Advantest Corp 誤設定検出機能を具備したｉｃ試験装置
JP3457626B2 (ja) * 2000-04-20 2003-10-20 Ｎｅｃエレクトロニクス株式会社 ジッタ検出回路
GB2379142B (en) * 2001-08-24 2004-11-17 Fujitsu Ltd Distribution of signals in high speed digital circuitry
KR20040081803A (ko) * 2002-02-21 2004-09-22 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 집적 회로
TWI229504B (en) * 2002-10-25 2005-03-11 Via Tech Inc Clock skew indicating apparatus for integrated circuit chip
FR2875311A1 (fr) * 2004-09-14 2006-03-17 St Microelectronics Sa Procede de detection du positionnement relatif de deux signaux et dispositif correspondant
JP4342503B2 (ja) * 2005-10-20 2009-10-14 富士通マイクロエレクトロニクス株式会社 半導体装置および半導体装置の検査方法
EP1950577A3 (de) * 2007-01-29 2012-01-11 Stmicroelectronics Sa Verfahren zur Integritätsüberprüfung einer Uhrwerkswelle
DE102007027069B3 (de) * 2007-06-12 2008-10-23 Texas Instruments Deutschland Gmbh Elektronische Vorrichtung und Verfahren zur chipintegrierten Zeitversatzmessung
WO2010087817A1 (en) 2009-01-27 2010-08-05 Agere Systems Inc. Critical-path circuit for performance monitoring
FR3066871A1 (fr) * 2017-05-24 2018-11-30 Stmicroelectronics (Rousset) Sas Dispositif logique de detection de fautes
FR3084488B1 (fr) 2018-07-24 2020-08-14 Stmicroelectronics (Grenoble 2) Sas Dispositif de detection d'une faute dans un circuit de propagation d'un signal d'horloge, et procede correspondant

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4072869A (en) * 1976-12-10 1978-02-07 Ncr Corporation Hazard-free clocked master/slave flip-flop
JPS59186415A (ja) * 1983-04-08 1984-10-23 テクトロニクス・インコ−ポレイテツド スキユ−検出器
US4623805A (en) * 1984-08-29 1986-11-18 Burroughs Corporation Automatic signal delay adjustment apparatus
JPS6417515A (en) * 1987-07-13 1989-01-20 Hitachi Ltd Phase comparator
JPH02105910A (ja) * 1988-10-14 1990-04-18 Hitachi Ltd 論理集積回路
US5095454A (en) * 1989-05-25 1992-03-10 Gateway Design Automation Corporation Method and apparatus for verifying timing during simulation of digital circuits
US5159279A (en) * 1990-11-27 1992-10-27 Dsc Communications Corporation Apparatus and method for detecting out-of-lock condition in a phase lock loop
US5313476A (en) * 1991-06-28 1994-05-17 International Business Machines Corporation Clock security ring
US5309111A (en) * 1992-06-26 1994-05-03 Thomson Consumer Electronics Apparatus for measuring skew timing errors
US5371417A (en) * 1993-07-02 1994-12-06 Tandem Computers Incorporated Multiple frequency output clock generator system
US5381416A (en) * 1993-11-08 1995-01-10 Unisys Corporation Detection of skew fault in a multiple clock system

Also Published As

Publication number Publication date
JPH07181234A (ja) 1995-07-21
DE69407529T2 (de) 1998-06-04
EP0648017A1 (de) 1995-04-12
EP0648017B1 (de) 1997-12-29
FR2711286A1 (fr) 1995-04-21
US5498983A (en) 1996-03-12
JP2657363B2 (ja) 1997-09-24
FR2711286B1 (fr) 1996-01-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee