DE69325751D1 - Verfahren zum Testen des Kontakts zwischen einem integrierten Baustein und einer Leiterplatte - Google Patents

Verfahren zum Testen des Kontakts zwischen einem integrierten Baustein und einer Leiterplatte

Info

Publication number
DE69325751D1
DE69325751D1 DE69325751T DE69325751T DE69325751D1 DE 69325751 D1 DE69325751 D1 DE 69325751D1 DE 69325751 T DE69325751 T DE 69325751T DE 69325751 T DE69325751 T DE 69325751T DE 69325751 D1 DE69325751 D1 DE 69325751D1
Authority
DE
Germany
Prior art keywords
testing
procedure
contact
circuit board
integrated module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69325751T
Other languages
English (en)
Other versions
DE69325751T2 (de
Inventor
Mark Alexander Laing
Robert John Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marconi Instruments Ltd
Original Assignee
Marconi Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Instruments Ltd filed Critical Marconi Instruments Ltd
Publication of DE69325751D1 publication Critical patent/DE69325751D1/de
Application granted granted Critical
Publication of DE69325751T2 publication Critical patent/DE69325751T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/315—Contactless testing by inductive methods
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/70—Testing of connections between components and printed circuit boards

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE69325751T 1992-06-15 1993-05-26 Verfahren zum Testen des Kontakts zwischen einem integrierten Baustein und einer Leiterplatte Expired - Fee Related DE69325751T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB929212646A GB9212646D0 (en) 1992-06-15 1992-06-15 A method of and equipment for testing the electrical conductivity of a connection

Publications (2)

Publication Number Publication Date
DE69325751D1 true DE69325751D1 (de) 1999-09-02
DE69325751T2 DE69325751T2 (de) 1999-11-18

Family

ID=10717097

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69325751T Expired - Fee Related DE69325751T2 (de) 1992-06-15 1993-05-26 Verfahren zum Testen des Kontakts zwischen einem integrierten Baustein und einer Leiterplatte

Country Status (4)

Country Link
US (1) US5399975A (de)
EP (1) EP0575061B1 (de)
DE (1) DE69325751T2 (de)
GB (1) GB9212646D0 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5631572A (en) * 1993-09-17 1997-05-20 Teradyne, Inc. Printed circuit board tester using magnetic induction
JP3228631B2 (ja) * 1993-12-24 2001-11-12 東京エレクトロン株式会社 テスタ
US5521513A (en) * 1994-10-25 1996-05-28 Teradyne Inc Manufacturing defect analyzer
US5736862A (en) * 1995-06-22 1998-04-07 Genrad, Inc. System for detecting faults in connections between integrated circuits and circuit board traces
KR0163688B1 (ko) * 1995-07-28 1999-03-20 전주범 내부회로 측정장치
US6005385A (en) * 1996-06-24 1999-12-21 Taiwan Semiconductor Manufacturing Company, Ltd. Test board circuit for detecting tester malfunction and protecting devices under test
US6124715A (en) * 1998-04-13 2000-09-26 Lucent Technologies, Inc. Testing of live circuit boards
US6351116B1 (en) * 1999-09-30 2002-02-26 Rockwell Automation Technologies, Inc. System and method for on-line hall sensor programming
CN1314975C (zh) * 2001-04-09 2007-05-09 皇家菲利浦电子有限公司 有电源测试接口的集成电路
US20030115502A1 (en) * 2001-12-14 2003-06-19 Smiths Industries Aerospace & Defense Systems, Inc. Method of restoring encapsulated integrated circuit devices
GB2394780B (en) * 2002-10-29 2006-06-14 Ifr Ltd A method of and apparatus for testing for integrated circuit contact defects
EP1613970A4 (de) * 2003-03-25 2006-12-13 Smiths Aerospace Inc Verfahren zum wiederherstellen verkapselter integrierter schaltungsbauelemente
DE102006045319A1 (de) * 2006-09-22 2008-04-03 Honeywell Regelsysteme Gmbh Verfahren und Anordnung zur Detektion einer Spule
CN105807211A (zh) * 2016-05-11 2016-07-27 上海华虹宏力半导体制造有限公司 个性化值快速写入方法以及集成电路测试方法
WO2020087363A1 (zh) 2018-10-31 2020-05-07 深圳市汇顶科技股份有限公司 测试系统

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2311903A1 (de) * 1973-03-09 1974-09-12 Siemens Ag Verfahren und einrichtung zur ortung von kurzschluessen in mehrlagenverdrahtungen
AU499847B2 (en) * 1975-09-05 1979-05-03 Lm ERICSSON PTY. LTD Testing a printed circuit board
US4186338A (en) * 1976-12-16 1980-01-29 Genrad, Inc. Phase change detection method of and apparatus for current-tracing the location of faults on printed circuit boards and similar systems
US4220917A (en) * 1978-07-31 1980-09-02 International Business Machines Corporation Test circuitry for module interconnection network
GB8423310D0 (en) * 1984-09-14 1984-10-17 Gec Avionics Electric circuit testing equipment
GB8428405D0 (en) * 1984-11-09 1984-12-19 Membrain Ltd Automatic test equipment
EP0306656A1 (de) * 1987-08-20 1989-03-15 Siemens Aktiengesellschaft Einrichtung zur Prüfung von IC-Bausteinen
US4779043A (en) * 1987-08-26 1988-10-18 Hewlett-Packard Company Reversed IC test device and method
DE3729500A1 (de) * 1987-09-03 1989-03-16 Siemens Ag Vorrichtung zur fehlersuche in elektronischen schaltungen
US4963824A (en) * 1988-11-04 1990-10-16 International Business Machines Corporation Diagnostics of a board containing a plurality of hybrid electronic components
US5059897A (en) * 1989-12-07 1991-10-22 Texas Instruments Incorporated Method and apparatus for testing passive substrates for integrated circuit mounting
US5254953A (en) * 1990-12-20 1993-10-19 Hewlett-Packard Company Identification of pin-open faults by capacitive coupling through the integrated circuit package

Also Published As

Publication number Publication date
US5399975A (en) 1995-03-21
GB9212646D0 (en) 1992-07-29
DE69325751T2 (de) 1999-11-18
EP0575061A1 (de) 1993-12-22
EP0575061B1 (de) 1999-07-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee