DE69229073T2 - Datenverarbeitungssystem - Google Patents

Datenverarbeitungssystem

Info

Publication number
DE69229073T2
DE69229073T2 DE69229073T DE69229073T DE69229073T2 DE 69229073 T2 DE69229073 T2 DE 69229073T2 DE 69229073 T DE69229073 T DE 69229073T DE 69229073 T DE69229073 T DE 69229073T DE 69229073 T2 DE69229073 T2 DE 69229073T2
Authority
DE
Germany
Prior art keywords
data processing
processing system
data
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69229073T
Other languages
English (en)
Other versions
DE69229073D1 (de
Inventor
Robert William Cooper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR International Inc
Original Assignee
NCR International Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR International Inc filed Critical NCR International Inc
Application granted granted Critical
Publication of DE69229073D1 publication Critical patent/DE69229073D1/de
Publication of DE69229073T2 publication Critical patent/DE69229073T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
DE69229073T 1991-02-22 1992-02-21 Datenverarbeitungssystem Expired - Lifetime DE69229073T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/659,861 US5579484A (en) 1991-02-22 1991-02-22 System for performing fast data accessing in multiply/accumulate operations while using a VRAM

Publications (2)

Publication Number Publication Date
DE69229073D1 DE69229073D1 (de) 1999-06-10
DE69229073T2 true DE69229073T2 (de) 1999-11-18

Family

ID=24647131

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69229073T Expired - Lifetime DE69229073T2 (de) 1991-02-22 1992-02-21 Datenverarbeitungssystem

Country Status (5)

Country Link
US (1) US5579484A (de)
EP (1) EP0500383B1 (de)
JP (1) JP3628339B2 (de)
CA (1) CA2055315C (de)
DE (1) DE69229073T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6138204A (en) * 1997-12-17 2000-10-24 Motorola, Inc. Multi bus access memory
US6728910B1 (en) * 2000-09-20 2004-04-27 Lsi Logic Corporation Memory testing for built-in self-repair system
US7171508B2 (en) * 2004-08-23 2007-01-30 Micron Technology, Inc. Dual port memory with asymmetric inputs and outputs, device, system and method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
US4745577A (en) * 1984-11-20 1988-05-17 Fujitsu Limited Semiconductor memory device with shift registers for high speed reading and writing
JPS62184559A (ja) * 1986-02-06 1987-08-12 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション デ−タ処理システム
US5148524A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporating on chip vector/image mode line modification
US5197140A (en) * 1989-11-17 1993-03-23 Texas Instruments Incorporated Sliced addressing multi-processor and method of operation

Also Published As

Publication number Publication date
CA2055315A1 (en) 1992-08-23
EP0500383A2 (de) 1992-08-26
EP0500383A3 (en) 1994-10-19
JPH06180684A (ja) 1994-06-28
CA2055315C (en) 1999-03-16
US5579484A (en) 1996-11-26
JP3628339B2 (ja) 2005-03-09
EP0500383B1 (de) 1999-05-06
DE69229073D1 (de) 1999-06-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: V. BEZOLD & SOZIEN, 80799 MUENCHEN