DE69218706D1 - Leitung mit geregelter Zeitverzögerung - Google Patents

Leitung mit geregelter Zeitverzögerung

Info

Publication number
DE69218706D1
DE69218706D1 DE69218706T DE69218706T DE69218706D1 DE 69218706 D1 DE69218706 D1 DE 69218706D1 DE 69218706 T DE69218706 T DE 69218706T DE 69218706 T DE69218706 T DE 69218706T DE 69218706 D1 DE69218706 D1 DE 69218706D1
Authority
DE
Germany
Prior art keywords
line
time delay
regulated time
regulated
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69218706T
Other languages
English (en)
Other versions
DE69218706T2 (de
Inventor
Kiyoshi Kase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Japan Ltd
Original Assignee
Nippon Motorola Ltd
Motorola Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Motorola Ltd, Motorola Japan Ltd filed Critical Nippon Motorola Ltd
Publication of DE69218706D1 publication Critical patent/DE69218706D1/de
Application granted granted Critical
Publication of DE69218706T2 publication Critical patent/DE69218706T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00097—Avoiding variations of delay using feedback, e.g. controlled by a PLL
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/0013—Avoiding variations of delay due to power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE1992618706 1991-09-16 1992-09-10 Leitung mit geregelter Zeitverzögerung Expired - Fee Related DE69218706T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US76065991A 1991-09-16 1991-09-16

Publications (2)

Publication Number Publication Date
DE69218706D1 true DE69218706D1 (de) 1997-05-07
DE69218706T2 DE69218706T2 (de) 1997-10-23

Family

ID=25059786

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1992618706 Expired - Fee Related DE69218706T2 (de) 1991-09-16 1992-09-10 Leitung mit geregelter Zeitverzögerung

Country Status (4)

Country Link
EP (1) EP0533402B1 (de)
JP (1) JPH05218829A (de)
DE (1) DE69218706T2 (de)
HK (1) HK1007221A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3961195B2 (ja) 2000-05-30 2007-08-22 株式会社東芝 半導体集積回路
JP3842560B2 (ja) * 2001-01-18 2006-11-08 東芝マイクロエレクトロニクス株式会社 半導体集積回路

Also Published As

Publication number Publication date
JPH05218829A (ja) 1993-08-27
DE69218706T2 (de) 1997-10-23
EP0533402B1 (de) 1997-04-02
HK1007221A1 (en) 1999-04-01
EP0533402A1 (de) 1993-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee