DE69132480T2 - Prozessor, der Speicherzugriffe parallel zu Cache-Speicherzugriffen durchführt und Verfahren dafür - Google Patents

Prozessor, der Speicherzugriffe parallel zu Cache-Speicherzugriffen durchführt und Verfahren dafür

Info

Publication number
DE69132480T2
DE69132480T2 DE69132480T DE69132480T DE69132480T2 DE 69132480 T2 DE69132480 T2 DE 69132480T2 DE 69132480 T DE69132480 T DE 69132480T DE 69132480 T DE69132480 T DE 69132480T DE 69132480 T2 DE69132480 T2 DE 69132480T2
Authority
DE
Germany
Prior art keywords
memory accesses
processor
parallel
method therefor
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69132480T
Other languages
English (en)
Other versions
DE69132480D1 (de
Inventor
Terry J Parks
D Matteson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dell USA LP
Original Assignee
Dell USA LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dell USA LP filed Critical Dell USA LP
Publication of DE69132480D1 publication Critical patent/DE69132480D1/de
Application granted granted Critical
Publication of DE69132480T2 publication Critical patent/DE69132480T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69132480T 1990-07-27 1991-07-25 Prozessor, der Speicherzugriffe parallel zu Cache-Speicherzugriffen durchführt und Verfahren dafür Expired - Lifetime DE69132480T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US55923090A 1990-07-27 1990-07-27

Publications (2)

Publication Number Publication Date
DE69132480D1 DE69132480D1 (de) 2001-01-04
DE69132480T2 true DE69132480T2 (de) 2001-06-13

Family

ID=24232815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132480T Expired - Lifetime DE69132480T2 (de) 1990-07-27 1991-07-25 Prozessor, der Speicherzugriffe parallel zu Cache-Speicherzugriffen durchführt und Verfahren dafür

Country Status (5)

Country Link
US (1) US5325508A (de)
EP (1) EP0468786B1 (de)
JP (1) JPH04233642A (de)
KR (1) KR920003163A (de)
DE (1) DE69132480T2 (de)

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US6892279B2 (en) * 2000-11-30 2005-05-10 Mosaid Technologies Incorporated Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency
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US6507893B2 (en) 2001-01-26 2003-01-14 Dell Products, L.P. System and method for time window access frequency based caching for memory controllers
US6487638B2 (en) * 2001-01-26 2002-11-26 Dell Products, L.P. System and method for time weighted access frequency based caching for memory controllers
US7240157B2 (en) * 2001-09-26 2007-07-03 Ati Technologies, Inc. System for handling memory requests and method thereof
US6718440B2 (en) * 2001-09-28 2004-04-06 Intel Corporation Memory access latency hiding with hint buffer
US6789169B2 (en) * 2001-10-04 2004-09-07 Micron Technology, Inc. Embedded DRAM cache memory and method having reduced latency
US7062610B2 (en) * 2002-09-30 2006-06-13 Advanced Micro Devices, Inc. Method and apparatus for reducing overhead in a data processing system with a cache
US7334102B1 (en) 2003-05-09 2008-02-19 Advanced Micro Devices, Inc. Apparatus and method for balanced spinlock support in NUMA systems
US20060031565A1 (en) * 2004-07-16 2006-02-09 Sundar Iyer High speed packet-buffering system
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EP2545424A4 (de) * 2010-03-09 2014-07-16 Happy Cloud Inc Datenstreaming für interaktive entscheidungsorientierte softwareanwendungen
WO2012015766A2 (en) 2010-07-28 2012-02-02 Rambus Inc. Cache memory that supports tagless addressing
US20120079348A1 (en) * 2010-09-24 2012-03-29 Helia Naeimi Data with appended crc and residue value and encoder/decoder for same
US8671221B2 (en) 2010-11-17 2014-03-11 Hola Networks Ltd. Method and system for increasing speed of domain name system resolution within a computing device
US8782053B2 (en) 2011-03-06 2014-07-15 Happy Cloud Inc. Data streaming for interactive decision-oriented software applications
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US10866897B2 (en) * 2016-09-26 2020-12-15 Samsung Electronics Co., Ltd. Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer

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Also Published As

Publication number Publication date
JPH04233642A (ja) 1992-08-21
DE69132480D1 (de) 2001-01-04
EP0468786B1 (de) 2000-11-29
US5325508A (en) 1994-06-28
EP0468786A2 (de) 1992-01-29
KR920003163A (ko) 1992-02-29
EP0468786A3 (en) 1992-02-26

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