DE69132005T2 - Vorrichtung und Verfahren für einen raumsparenden Adressenübersetzungspuffer für inhaltsadressierbaren Speicher - Google Patents

Vorrichtung und Verfahren für einen raumsparenden Adressenübersetzungspuffer für inhaltsadressierbaren Speicher

Info

Publication number
DE69132005T2
DE69132005T2 DE69132005T DE69132005T DE69132005T2 DE 69132005 T2 DE69132005 T2 DE 69132005T2 DE 69132005 T DE69132005 T DE 69132005T DE 69132005 T DE69132005 T DE 69132005T DE 69132005 T2 DE69132005 T2 DE 69132005T2
Authority
DE
Germany
Prior art keywords
space
address translation
content addressable
translation buffer
addressable memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69132005T
Other languages
English (en)
Other versions
DE69132005D1 (de
Inventor
Peter A Mehring
Robert D Becker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE69132005D1 publication Critical patent/DE69132005D1/de
Publication of DE69132005T2 publication Critical patent/DE69132005T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/652—Page size control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69132005T 1990-12-18 1991-12-03 Vorrichtung und Verfahren für einen raumsparenden Adressenübersetzungspuffer für inhaltsadressierbaren Speicher Expired - Fee Related DE69132005T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/629,258 US5222222A (en) 1990-12-18 1990-12-18 Apparatus and method for a space saving translation lookaside buffer for content addressable memory

Publications (2)

Publication Number Publication Date
DE69132005D1 DE69132005D1 (de) 2000-04-06
DE69132005T2 true DE69132005T2 (de) 2000-10-19

Family

ID=24522242

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69132005T Expired - Fee Related DE69132005T2 (de) 1990-12-18 1991-12-03 Vorrichtung und Verfahren für einen raumsparenden Adressenübersetzungspuffer für inhaltsadressierbaren Speicher

Country Status (6)

Country Link
US (1) US5222222A (de)
EP (1) EP0491498B1 (de)
JP (1) JP3278748B2 (de)
KR (1) KR960001944B1 (de)
CA (1) CA2057403C (de)
DE (1) DE69132005T2 (de)

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GB2251102B (en) * 1990-12-21 1995-03-15 Sun Microsystems Inc Translation lookaside buffer
US5420993A (en) * 1991-06-13 1995-05-30 Unisys Corporation Extended address translation system for pointer updating in paged memory systems
KR940005781B1 (ko) * 1992-02-25 1994-06-23 현대전자산업 주식회사 메모리 매너지먼트 유니트(mmu)
US5440707A (en) * 1992-04-29 1995-08-08 Sun Microsystems, Inc. Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle
US5450558A (en) * 1992-05-27 1995-09-12 Hewlett-Packard Company System for translating virtual address to real address by duplicating mask information in real page number corresponds to block entry of virtual page number
DE69315630T2 (de) * 1992-07-23 1998-07-16 Rockwell International Corp Datenzugriff in einem RISC-Digitalsignalprozessor
US5450562A (en) * 1992-10-19 1995-09-12 Hewlett-Packard Company Cache-based data compression/decompression
US5568415A (en) * 1993-02-19 1996-10-22 Digital Equipment Corporation Content addressable memory having a pair of memory cells storing don't care states for address translation
US6000008A (en) * 1993-03-11 1999-12-07 Cabletron Systems, Inc. Method and apparatus for matching data items of variable length in a content addressable memory
US5483644A (en) * 1993-04-15 1996-01-09 Vlsi Technology, Inc. Method for increasing cacheable address space in a second level cache
DE19516949A1 (de) * 1994-05-11 1996-02-15 Gmd Gmbh Speichervorrichtung zum Speichern von Daten
JP3740195B2 (ja) * 1994-09-09 2006-02-01 株式会社ルネサステクノロジ データ処理装置
US5963984A (en) * 1994-11-08 1999-10-05 National Semiconductor Corporation Address translation unit employing programmable page size
US5584013A (en) * 1994-12-09 1996-12-10 International Business Machines Corporation Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
US5682495A (en) * 1994-12-09 1997-10-28 International Business Machines Corporation Fully associative address translation buffer having separate segment and page invalidation
US5715420A (en) * 1995-02-10 1998-02-03 International Business Machines Corporation Method and system for efficient memory management in a data processing system utilizing a dual mode translation lookaside buffer
US5680566A (en) * 1995-03-03 1997-10-21 Hal Computer Systems, Inc. Lookaside buffer for inputting multiple address translations in a computer system
US6069638A (en) * 1997-06-25 2000-05-30 Micron Electronics, Inc. System for accelerated graphics port address remapping interface to main memory
US6249853B1 (en) 1997-06-25 2001-06-19 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6282625B1 (en) 1997-06-25 2001-08-28 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6078987A (en) * 1997-09-30 2000-06-20 Sun Microsystems, Inc. Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals
US5936873A (en) * 1997-09-30 1999-08-10 Sun Microsystems, Inc. Single ended match sense amplifier
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US6252612B1 (en) 1997-12-30 2001-06-26 Micron Electronics, Inc. Accelerated graphics port for multiple memory controller computer system
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6243775B1 (en) 1998-01-20 2001-06-05 Micron Technology, Inc. System for extending the available number of configuration registers
US6108733A (en) * 1998-01-20 2000-08-22 Micron Technology, Inc. Method for extending the available number of configuration registers
US6272576B1 (en) 1998-01-20 2001-08-07 Micron Technology, Inc. Method for extending the available number of configuration registers
KR100590751B1 (ko) * 1999-02-23 2006-06-15 삼성전자주식회사 데이터라인크기변경시엔트리갯수가동일한캐시메모리시스템
US6327646B1 (en) * 1999-03-12 2001-12-04 Intel Corporation Translation look-aside buffer utilizing high-order bits for fast access
US6362990B1 (en) 1999-09-10 2002-03-26 Sibercore Technologies Three port content addressable memory device and methods for implementing the same
US6392910B1 (en) * 1999-09-10 2002-05-21 Sibercore Technologies, Inc. Priority encoder with multiple match function for content addressable memories and methods for implementing the same
US6553453B1 (en) 1999-09-10 2003-04-22 Sibercore Technologies, Inc. Variable width content addressable memory device for searching variable width data
KR100587148B1 (ko) * 2000-12-30 2006-06-07 매그나칩 반도체 유한회사 캠 셀 구조
US6901476B2 (en) * 2002-05-06 2005-05-31 Hywire Ltd. Variable key type search engine and method therefor
US20050182903A1 (en) * 2004-02-12 2005-08-18 Mips Technologies, Inc. Apparatus and method for preventing duplicate matching entries in a translation lookaside buffer
US20050182912A1 (en) * 2004-02-12 2005-08-18 International Business Machines Corporation Method of effective to real address translation for a multi-threaded microprocessor
US7167970B2 (en) * 2004-05-24 2007-01-23 Sun Microsystems, Inc. Translating loads for accelerating virtualized partition
KR100703164B1 (ko) * 2005-07-12 2007-04-06 삼성전자주식회사 데이터 처리장치 및 그 제어방법
US8468297B2 (en) 2010-06-23 2013-06-18 International Business Machines Corporation Content addressable memory system
US9092359B2 (en) 2012-06-14 2015-07-28 International Business Machines Corporation Identification and consolidation of page table entries
US9811472B2 (en) * 2012-06-14 2017-11-07 International Business Machines Corporation Radix table translation of memory
US9753860B2 (en) 2012-06-14 2017-09-05 International Business Machines Corporation Page table entry consolidation
US11216385B2 (en) 2019-05-15 2022-01-04 Samsung Electronics Co., Ltd. Application processor, system-on chip and method of operating memory management unit

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Publication number Priority date Publication date Assignee Title
FR10582E (fr) * 1970-06-29 1909-07-30 Paul Alexis Victor Lerolle Jeu de serrures avec passe-partout
US4285040A (en) * 1977-11-04 1981-08-18 Sperry Corporation Dual mode virtual-to-real address translation mechanism
US4680700A (en) * 1983-12-07 1987-07-14 International Business Machines Corporation Virtual memory address translation mechanism with combined hash address table and inverted page table
JPH0685156B2 (ja) * 1985-05-24 1994-10-26 株式会社日立製作所 アドレス変換装置
JPS62237547A (ja) * 1986-04-09 1987-10-17 Hitachi Ltd アドレス変換方式
US4914577A (en) * 1987-07-16 1990-04-03 Icon International, Inc. Dynamic memory management system and method
US5058003A (en) * 1988-12-15 1991-10-15 International Business Machines Corporation Virtual storage dynamic address translation mechanism for multiple-sized pages
US5133058A (en) * 1989-09-18 1992-07-21 Sun Microsystems, Inc. Page-tagging translation look-aside buffer for a computer memory system

Also Published As

Publication number Publication date
CA2057403A1 (en) 1992-06-19
DE69132005D1 (de) 2000-04-06
CA2057403C (en) 2001-02-27
KR960001944B1 (ko) 1996-02-08
US5222222A (en) 1993-06-22
JPH04352256A (ja) 1992-12-07
KR920013131A (ko) 1992-07-28
EP0491498A3 (en) 1993-01-13
EP0491498A2 (de) 1992-06-24
EP0491498B1 (de) 2000-03-01
JP3278748B2 (ja) 2002-04-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee