DE69130553D1 - Arithmetisch logische Einheit - Google Patents

Arithmetisch logische Einheit

Info

Publication number
DE69130553D1
DE69130553D1 DE69130553T DE69130553T DE69130553D1 DE 69130553 D1 DE69130553 D1 DE 69130553D1 DE 69130553 T DE69130553 T DE 69130553T DE 69130553 T DE69130553 T DE 69130553T DE 69130553 D1 DE69130553 D1 DE 69130553D1
Authority
DE
Germany
Prior art keywords
arithmetically
logical unit
logical
unit
arithmetically logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130553T
Other languages
English (en)
Other versions
DE69130553T2 (de
Inventor
Akio Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69130553D1 publication Critical patent/DE69130553D1/de
Publication of DE69130553T2 publication Critical patent/DE69130553T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/544—Indexing scheme relating to group G06F7/544
    • G06F2207/5442—Absolute difference

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Image Processing (AREA)
DE69130553T 1990-07-27 1991-07-29 Arithmetisch logische Einheit Expired - Fee Related DE69130553T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2199550A JPH0484317A (ja) 1990-07-27 1990-07-27 算術論理演算ユニット

Publications (2)

Publication Number Publication Date
DE69130553D1 true DE69130553D1 (de) 1999-01-14
DE69130553T2 DE69130553T2 (de) 1999-07-15

Family

ID=16409694

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130553T Expired - Fee Related DE69130553T2 (de) 1990-07-27 1991-07-29 Arithmetisch logische Einheit

Country Status (4)

Country Link
US (1) US5305249A (de)
EP (1) EP0468534B1 (de)
JP (1) JPH0484317A (de)
DE (1) DE69130553T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2270400B (en) * 1992-09-08 1996-09-18 Sony Corp Digital audio mixer
JP3546437B2 (ja) * 1993-03-31 2004-07-28 ソニー株式会社 適応形ビデオ信号演算処理装置
US5563813A (en) * 1994-06-01 1996-10-08 Industrial Technology Research Institute Area/time-efficient motion estimation micro core
US5880979A (en) * 1995-12-21 1999-03-09 Intel Corporation System for providing the absolute difference of unsigned values
US5875121A (en) * 1996-08-06 1999-02-23 Hewlett-Packard Company Register selection system and method
US5793655A (en) * 1996-10-23 1998-08-11 Zapex Technologies, Inc. Sum of the absolute values generator
US6584156B1 (en) * 1998-07-17 2003-06-24 Stream Machine Company LSI Architecture and implementation of MPEG video codec
US20030188134A1 (en) * 2002-03-28 2003-10-02 Intel Corporation Combined addition/subtraction instruction with a flexible and dynamic source selection mechanism
US7817719B2 (en) * 2005-05-31 2010-10-19 Atmel Corporation System for increasing the speed of a sum-of-absolute-differences operation
US8015229B2 (en) * 2005-06-01 2011-09-06 Atmel Corporation Apparatus and method for performing efficient multiply-accumulate operations in microprocessors

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3814925A (en) * 1972-10-30 1974-06-04 Amdahl Corp Dual output adder and method of addition for concurrently forming the differences a{31 b and b{31 a
US4849921A (en) * 1985-06-19 1989-07-18 Nec Corporation Arithmetic circuit for calculating the absolute value of the difference between a pair of input signals
JPS6395533A (ja) * 1986-10-09 1988-04-26 Mitsubishi Electric Corp 論理回路
JPH073653B2 (ja) * 1987-06-30 1995-01-18 三菱電機株式会社 シフタ
JPH01204138A (ja) * 1988-02-09 1989-08-16 Nec Corp 演算回路

Also Published As

Publication number Publication date
EP0468534A3 (en) 1993-01-07
US5305249A (en) 1994-04-19
DE69130553T2 (de) 1999-07-15
JPH0484317A (ja) 1992-03-17
EP0468534B1 (de) 1998-12-02
EP0468534A2 (de) 1992-01-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee