DE69128615D1 - Sendesteuerungssystem für eingangs/ausgangsbefehle in einem datenverarbeitungssystem - Google Patents

Sendesteuerungssystem für eingangs/ausgangsbefehle in einem datenverarbeitungssystem

Info

Publication number
DE69128615D1
DE69128615D1 DE69128615T DE69128615T DE69128615D1 DE 69128615 D1 DE69128615 D1 DE 69128615D1 DE 69128615 T DE69128615 T DE 69128615T DE 69128615 T DE69128615 T DE 69128615T DE 69128615 D1 DE69128615 D1 DE 69128615D1
Authority
DE
Germany
Prior art keywords
input
data processing
transmit control
output commands
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69128615T
Other languages
English (en)
Other versions
DE69128615T2 (de
Inventor
Yuji Fujitsu Limited Hidaka
Makoto Fujitsu Limited Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69128615D1 publication Critical patent/DE69128615D1/de
Publication of DE69128615T2 publication Critical patent/DE69128615T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
DE69128615T 1990-10-03 1991-10-02 Sendesteuerungssystem für eingangs/ausgangsbefehle in einem datenverarbeitungssystem Expired - Fee Related DE69128615T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26588590 1990-10-03
PCT/JP1991/001325 WO1992006057A1 (fr) 1990-10-03 1991-10-02 Systeme servant a commander l'emission d'instructions d'entree/sortie dans un systeme de traitement de donnees

Publications (2)

Publication Number Publication Date
DE69128615D1 true DE69128615D1 (de) 1998-02-12
DE69128615T2 DE69128615T2 (de) 1998-04-23

Family

ID=17423454

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69128615T Expired - Fee Related DE69128615T2 (de) 1990-10-03 1991-10-02 Sendesteuerungssystem für eingangs/ausgangsbefehle in einem datenverarbeitungssystem

Country Status (6)

Country Link
US (1) US5363488A (de)
EP (1) EP0503092B1 (de)
AU (1) AU639150B2 (de)
CA (1) CA2070285C (de)
DE (1) DE69128615T2 (de)
WO (1) WO1992006057A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69325769T2 (de) * 1992-11-04 2000-03-23 Digital Equipment Corp Erkennung von Befehlssynchronisationsfehlern
US5659794A (en) * 1995-03-31 1997-08-19 Unisys Corporation System architecture for improved network input/output processing
JP4111472B2 (ja) * 1998-05-15 2008-07-02 キヤノン株式会社 通信制御方法及び装置及び通信システム
JP4109770B2 (ja) * 1998-12-02 2008-07-02 キヤノン株式会社 通信制御方法及び機器
JP5446464B2 (ja) * 2009-05-26 2014-03-19 富士通セミコンダクター株式会社 情報処理システム及びデータ転送方法
TWI526838B (zh) * 2013-02-27 2016-03-21 東芝股份有限公司 記憶體裝置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61288232A (ja) * 1985-06-17 1986-12-18 Fujitsu Ltd 出力命令制御方式
JPH0792761B2 (ja) * 1985-07-31 1995-10-09 株式会社日立製作所 仮想計算機システムの入出力制御方法
JPH02208740A (ja) * 1989-02-09 1990-08-20 Fujitsu Ltd 仮想計算機制御方式
US5220653A (en) * 1990-10-26 1993-06-15 International Business Machines Corporation Scheduling input/output operations in multitasking systems

Also Published As

Publication number Publication date
EP0503092A4 (en) 1993-03-31
EP0503092A1 (de) 1992-09-16
DE69128615T2 (de) 1998-04-23
CA2070285C (en) 1998-04-07
EP0503092B1 (de) 1998-01-07
CA2070285A1 (en) 1992-04-04
WO1992006057A1 (fr) 1992-04-16
AU8650491A (en) 1992-04-28
AU639150B2 (en) 1993-07-15
US5363488A (en) 1994-11-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee