DE69126924D1 - Effiziente Fehlererkennung in einer VLSI-zentralen Verarbeitungseinheit - Google Patents
Effiziente Fehlererkennung in einer VLSI-zentralen VerarbeitungseinheitInfo
- Publication number
- DE69126924D1 DE69126924D1 DE69126924T DE69126924T DE69126924D1 DE 69126924 D1 DE69126924 D1 DE 69126924D1 DE 69126924 T DE69126924 T DE 69126924T DE 69126924 T DE69126924 T DE 69126924T DE 69126924 D1 DE69126924 D1 DE 69126924D1
- Authority
- DE
- Germany
- Prior art keywords
- vlsi
- processing unit
- central processing
- error detection
- efficient error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/546,204 US5195101A (en) | 1990-06-28 | 1990-06-28 | Efficient error detection in a vlsi central processing unit |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69126924D1 true DE69126924D1 (de) | 1997-09-04 |
DE69126924T2 DE69126924T2 (de) | 1998-03-12 |
Family
ID=24179314
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69126924T Expired - Fee Related DE69126924T2 (de) | 1990-06-28 | 1991-06-20 | Effiziente Fehlererkennung in einer VLSI-zentralen Verarbeitungseinheit |
Country Status (4)
Country | Link |
---|---|
US (1) | US5195101A (de) |
EP (1) | EP0463573B1 (de) |
CA (1) | CA2041219C (de) |
DE (1) | DE69126924T2 (de) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04290144A (ja) * | 1991-03-19 | 1992-10-14 | Hitachi Ltd | メモリ拡張方式 |
US5649090A (en) * | 1991-05-31 | 1997-07-15 | Bull Hn Information Systems Inc. | Fault tolerant multiprocessor computer system |
US5434997A (en) * | 1992-10-02 | 1995-07-18 | Compaq Computer Corp. | Method and apparatus for testing and debugging a tightly coupled mirrored processing system |
US5435000A (en) * | 1993-05-19 | 1995-07-18 | Bull Hn Information Systems Inc. | Central processing unit using dual basic processing units and combined result bus |
US5440724A (en) * | 1993-06-17 | 1995-08-08 | Bull Hn Information Systems Inc. | Central processing unit using dual basic processing units and combined result bus and incorporating means for obtaining access to internal BPU test signals |
US5408651A (en) * | 1993-09-27 | 1995-04-18 | Bull Hn Information Systems Inc. | Store "undo" for cache store error recovery |
US5422837A (en) * | 1993-12-14 | 1995-06-06 | Bull Hn Information Systems Inc. | Apparatus for detecting differences between double precision results produced by dual processing units operating in parallel |
US5535405A (en) * | 1993-12-23 | 1996-07-09 | Unisys Corporation | Microsequencer bus controller system |
US5495579A (en) * | 1994-03-25 | 1996-02-27 | Bull Hn Information Systems Inc. | Central processor with duplicate basic processing units employing multiplexed cache store control signals to reduce inter-unit conductor count |
US5515529A (en) * | 1994-03-25 | 1996-05-07 | Bull Hn Information Syst | Central processor with duplicate basic processing units employing multiplexed data signals to reduce inter-unit conductor count |
US5630055A (en) * | 1995-05-05 | 1997-05-13 | Digital Equipment Corporation | Autonomous pipeline reconfiguration for continuous error correction for fills from tertiary cache or memory |
US5894564A (en) * | 1995-06-07 | 1999-04-13 | International Business Machines Corporation | System for identifying memory segment bounded by previously accessed memory locations within data block and transferring thereof only when the segment has been changed |
US5740350A (en) * | 1995-06-30 | 1998-04-14 | Bull Hn Information Systems Inc. | Reconfigurable computer system |
US5895485A (en) * | 1997-02-24 | 1999-04-20 | Eccs, Inc. | Method and device using a redundant cache for preventing the loss of dirty data |
US7213170B2 (en) * | 2003-09-10 | 2007-05-01 | Hewlett-Packard Development Company, L.P. | Opportunistic CPU functional testing with hardware compare |
US7206969B2 (en) * | 2003-09-10 | 2007-04-17 | Hewlett-Packard Development Company, L.P. | Opportunistic pattern-based CPU functional testing |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4456952A (en) * | 1977-03-17 | 1984-06-26 | Honeywell Information Systems Inc. | Data processing system having redundant control processors for fault detection |
US4358823A (en) * | 1977-03-25 | 1982-11-09 | Trw, Inc. | Double redundant processor |
CA1118101A (en) * | 1977-06-02 | 1982-02-09 | Jerry Doniger | Digital flight guidance system |
US4768148A (en) * | 1986-06-27 | 1988-08-30 | Honeywell Bull Inc. | Read in process memory apparatus |
IT1213344B (it) * | 1986-09-17 | 1989-12-20 | Honoywell Information Systems | Architettura di calcolatore a tolleranza di guasto. |
US4811215A (en) * | 1986-12-12 | 1989-03-07 | Intergraph Corporation | Instruction execution accelerator for a pipelined digital machine with virtual memory |
JPH0833842B2 (ja) * | 1987-05-01 | 1996-03-29 | 株式会社日立製作所 | 論理演算装置 |
JPH0821238B2 (ja) * | 1987-11-12 | 1996-03-04 | 三菱電機株式会社 | 半導体記憶装置 |
-
1990
- 1990-06-28 US US07/546,204 patent/US5195101A/en not_active Expired - Lifetime
-
1991
- 1991-04-25 CA CA002041219A patent/CA2041219C/en not_active Expired - Fee Related
- 1991-06-20 EP EP91110179A patent/EP0463573B1/de not_active Expired - Lifetime
- 1991-06-20 DE DE69126924T patent/DE69126924T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA2041219A1 (en) | 1991-12-29 |
EP0463573A2 (de) | 1992-01-02 |
DE69126924T2 (de) | 1998-03-12 |
EP0463573A3 (en) | 1993-02-03 |
US5195101A (en) | 1993-03-16 |
EP0463573B1 (de) | 1997-07-23 |
CA2041219C (en) | 1994-07-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |