DE69124285D1 - Datenverarbeitungssystem mit einem Eingangs-/Ausgangswegetrennmechanismus und Verfahren zur Steuerung des Datenverarbeitungssystems - Google Patents
Datenverarbeitungssystem mit einem Eingangs-/Ausgangswegetrennmechanismus und Verfahren zur Steuerung des DatenverarbeitungssystemsInfo
- Publication number
- DE69124285D1 DE69124285D1 DE69124285T DE69124285T DE69124285D1 DE 69124285 D1 DE69124285 D1 DE 69124285D1 DE 69124285 T DE69124285 T DE 69124285T DE 69124285 T DE69124285 T DE 69124285T DE 69124285 D1 DE69124285 D1 DE 69124285D1
- Authority
- DE
- Germany
- Prior art keywords
- data processing
- processing system
- controlling
- input
- separation mechanism
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Hardware Redundancy (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2128324A JP2716571B2 (ja) | 1990-05-18 | 1990-05-18 | 二重化データ保全装置 |
JP17106890A JPH0460750A (ja) | 1990-06-28 | 1990-06-28 | クラスタ停止装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69124285D1 true DE69124285D1 (de) | 1997-03-06 |
DE69124285T2 DE69124285T2 (de) | 1997-08-14 |
Family
ID=26464026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69124285T Expired - Fee Related DE69124285T2 (de) | 1990-05-18 | 1991-05-15 | Datenverarbeitungssystem mit einem Eingangs-/Ausgangswegetrennmechanismus und Verfahren zur Steuerung des Datenverarbeitungssystems |
Country Status (3)
Country | Link |
---|---|
US (2) | US5548743A (de) |
EP (1) | EP0457308B1 (de) |
DE (1) | DE69124285T2 (de) |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5430868A (en) * | 1993-09-23 | 1995-07-04 | At&T Corp. | Shared memory with benign failure modes |
US5867655A (en) * | 1993-12-08 | 1999-02-02 | Packard Bell Nec | Method to store privileged data within the primary CPU memory space |
EP0764302B1 (de) * | 1994-06-10 | 1998-12-02 | Texas Micro Inc. | Hauptspeichervorrichtung und wiederanlaufkennzeichnungsverfahren für ein fehlertolerantes rechnersystem |
FR2724026B1 (fr) * | 1994-08-29 | 1996-10-18 | Aerospatiale | Procede et dispositif pour l'identification de pannes dans un systeme complexe |
US5864657A (en) * | 1995-11-29 | 1999-01-26 | Texas Micro, Inc. | Main memory system and checkpointing protocol for fault-tolerant computer system |
US5745672A (en) * | 1995-11-29 | 1998-04-28 | Texas Micro, Inc. | Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer |
US5978933A (en) * | 1996-01-11 | 1999-11-02 | Hewlett-Packard Company | Generic fault tolerant platform |
JPH1185659A (ja) * | 1997-09-03 | 1999-03-30 | Hitachi Ltd | ディスク制御装置及びこれを用いた記憶装置 |
JP3866426B2 (ja) * | 1998-11-05 | 2007-01-10 | 日本電気株式会社 | クラスタ計算機におけるメモリ障害処理方法及びクラスタ計算機 |
US6363495B1 (en) | 1999-01-19 | 2002-03-26 | International Business Machines Corporation | Method and apparatus for partition resolution in clustered computer systems |
US6647301B1 (en) * | 1999-04-22 | 2003-11-11 | Dow Global Technologies Inc. | Process control system with integrated safety control system |
WO2001016737A2 (en) * | 1999-08-31 | 2001-03-08 | Times N Systems, Inc. | Cache-coherent shared-memory cluster |
US6594785B1 (en) * | 2000-04-28 | 2003-07-15 | Unisys Corporation | System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions |
US6715059B2 (en) | 2000-07-26 | 2004-03-30 | Tas Holdings, Inc. | Methods and systems for a shared memory unit with extendable functions |
US20020029334A1 (en) * | 2000-07-26 | 2002-03-07 | West Karlon K. | High availability shared memory system |
US20020013822A1 (en) * | 2000-07-26 | 2002-01-31 | West Karlon K. | Shared as needed programming model |
US6892298B2 (en) | 2000-07-26 | 2005-05-10 | Times N Systems, Inc. | Load/store micropacket handling system |
US6675277B2 (en) | 2000-07-26 | 2004-01-06 | Tns Holdings, Inc. | Method and apparatus for demand usable adapter memory access management |
US6665777B2 (en) | 2000-07-26 | 2003-12-16 | Tns Holdings, Inc. | Method, apparatus, network, and kit for multiple block sequential memory management |
US6782440B2 (en) | 2000-07-26 | 2004-08-24 | T.N.S. Holdings, Inc. | Resource locking and thread synchronization in a multiprocessor environment |
SE524110C2 (sv) * | 2001-06-06 | 2004-06-29 | Kvaser Consultant Ab | Anordning och förfarande vid system med lokalt utplacerade modulenheter samt kontaktenhet för anslutning av sådan modulenhet |
US6944787B2 (en) * | 2001-10-01 | 2005-09-13 | International Business Machines Corporation | System-managed duplexing of coupling facility structures |
JP2003330905A (ja) * | 2002-05-14 | 2003-11-21 | Nec Corp | コンピュータシステム |
US7395337B2 (en) * | 2002-08-29 | 2008-07-01 | International Business Machines Corporation | Method, system, and program for establishing and requesting status on a computational resource |
JP2005203064A (ja) * | 2004-01-19 | 2005-07-28 | Toshiba Corp | 半導体記憶装置 |
US7707179B2 (en) * | 2004-04-23 | 2010-04-27 | Waratek Pty Limited | Multiple computer architecture with synchronization |
US20060253844A1 (en) | 2005-04-21 | 2006-11-09 | Holt John M | Computer architecture and method of operation for multi-computer distributed processing with initialization of objects |
US20050262513A1 (en) * | 2004-04-23 | 2005-11-24 | Waratek Pty Limited | Modified computer architecture with initialization of objects |
US20050257219A1 (en) * | 2004-04-23 | 2005-11-17 | Holt John M | Multiple computer architecture with replicated memory fields |
US7844665B2 (en) * | 2004-04-23 | 2010-11-30 | Waratek Pty Ltd. | Modified computer architecture having coordinated deletion of corresponding replicated memory locations among plural computers |
US7849452B2 (en) * | 2004-04-23 | 2010-12-07 | Waratek Pty Ltd. | Modification of computer applications at load time for distributed execution |
US20060095483A1 (en) * | 2004-04-23 | 2006-05-04 | Waratek Pty Limited | Modified computer architecture with finalization of objects |
JP4387968B2 (ja) * | 2005-03-28 | 2009-12-24 | 富士通株式会社 | 障害検出装置および障害検出方法 |
US7757015B2 (en) * | 2005-09-13 | 2010-07-13 | International Business Machines Corporation | Device, method and computer program product readable medium for determining the identity of a component |
US7660960B2 (en) * | 2005-10-25 | 2010-02-09 | Waratek Pty, Ltd. | Modified machine architecture with partial memory updating |
US7849369B2 (en) * | 2005-10-25 | 2010-12-07 | Waratek Pty Ltd. | Failure resistant multiple computer system and method |
US7761670B2 (en) * | 2005-10-25 | 2010-07-20 | Waratek Pty Limited | Modified machine architecture with advanced synchronization |
US8015236B2 (en) * | 2005-10-25 | 2011-09-06 | Waratek Pty. Ltd. | Replication of objects having non-primitive fields, especially addresses |
US20070100828A1 (en) * | 2005-10-25 | 2007-05-03 | Holt John M | Modified machine architecture with machine redundancy |
US7958322B2 (en) * | 2005-10-25 | 2011-06-07 | Waratek Pty Ltd | Multiple machine architecture with overhead reduction |
WO2008040079A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Multiple network connections for multiple computers |
WO2008040082A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Multiple computer system with dual mode redundancy architecture |
US7739349B2 (en) * | 2006-10-05 | 2010-06-15 | Waratek Pty Limited | Synchronization with partial memory replication |
WO2008040063A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Multi-path switching networks |
WO2008040083A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Adding one or more computers to a multiple computer system |
US8090926B2 (en) * | 2006-10-05 | 2012-01-03 | Waratek Pty Ltd. | Hybrid replicated shared memory |
US20100121935A1 (en) * | 2006-10-05 | 2010-05-13 | Holt John M | Hybrid replicated shared memory |
WO2008040066A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Redundant multiple computer architecture |
WO2008040085A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Network protocol for network communications |
WO2008040065A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Contention detection and resolution |
US20080126503A1 (en) * | 2006-10-05 | 2008-05-29 | Holt John M | Contention resolution with echo cancellation |
US20100054254A1 (en) * | 2006-10-05 | 2010-03-04 | Holt John M | Asynchronous data transmission |
WO2008040064A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Switch protocol for network communications |
US20080133859A1 (en) * | 2006-10-05 | 2008-06-05 | Holt John M | Advanced synchronization and contention resolution |
US20080120477A1 (en) * | 2006-10-05 | 2008-05-22 | Holt John M | Contention detection with modified message format |
WO2008040081A1 (en) * | 2006-10-05 | 2008-04-10 | Waratek Pty Limited | Job scheduling amongst multiple computers |
US20080120478A1 (en) * | 2006-10-05 | 2008-05-22 | Holt John M | Advanced synchronization and contention resolution |
US7962697B2 (en) * | 2006-10-05 | 2011-06-14 | Waratek Pty Limited | Contention detection |
US20080126506A1 (en) * | 2006-10-05 | 2008-05-29 | Holt John M | Multiple computer system with redundancy architecture |
JP5318768B2 (ja) * | 2006-10-05 | 2013-10-16 | ワラテック プロプライエタリー リミテッド | 高度な競合検出 |
US20080140863A1 (en) * | 2006-10-05 | 2008-06-12 | Holt John M | Multiple communication networks for multiple computers |
US20080133689A1 (en) * | 2006-10-05 | 2008-06-05 | Holt John M | Silent memory reclamation |
US20080126372A1 (en) * | 2006-10-05 | 2008-05-29 | Holt John M | Cyclic redundant multiple computer architecture |
US20080140975A1 (en) * | 2006-10-05 | 2008-06-12 | Holt John M | Contention detection with data consolidation |
US20080250221A1 (en) * | 2006-10-09 | 2008-10-09 | Holt John M | Contention detection with data consolidation |
US8316190B2 (en) * | 2007-04-06 | 2012-11-20 | Waratek Pty. Ltd. | Computer architecture and method of operation for multi-computer distributed processing having redundant array of independent systems with replicated memory and code striping |
EP2555116A1 (de) * | 2010-03-31 | 2013-02-06 | Fujitsu Limited | Multicluster-system |
CN102455878A (zh) * | 2010-10-19 | 2012-05-16 | 英业达股份有限公司 | 动态磁盘访问方法 |
CN114385247A (zh) * | 2020-10-21 | 2022-04-22 | 环达电脑(上海)有限公司 | 开机方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3668644A (en) * | 1970-02-09 | 1972-06-06 | Burroughs Corp | Failsafe memory system |
DE2117128A1 (de) * | 1971-04-07 | 1972-10-19 | Siemens Ag | Verfahren zum Ein- und Ausschalten von Systemeinheiten in einem modular aufgebauten Verarbeitungssystem |
BE789828A (nl) * | 1972-10-09 | 1973-04-09 | Bell Telephone Mfg | Gegevensverwerkend besturingsstelsel. |
JPS52123137A (en) * | 1976-04-09 | 1977-10-17 | Hitachi Ltd | Duplication memory control unit |
US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
JPS5914062A (ja) * | 1982-07-15 | 1984-01-24 | Hitachi Ltd | 二重化共有メモリ制御方法 |
US4608631A (en) * | 1982-09-03 | 1986-08-26 | Sequoia Systems, Inc. | Modular computer system |
US4546454A (en) * | 1982-11-05 | 1985-10-08 | Seeq Technology, Inc. | Non-volatile memory cell fuse element |
DE3334773A1 (de) * | 1983-09-26 | 1984-11-08 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum betrieb eines in normalbetriebszeit parallel betriebenen speicherblockpaares |
DE3481872D1 (de) * | 1984-12-31 | 1990-05-10 | Ibm | Geraet zur erkennung von ausserbetriebzustaenden bei einem nichtbedienten unterbrechungsgesteuerten prozessor. |
US4757442A (en) * | 1985-06-17 | 1988-07-12 | Nec Corporation | Re-synchronization system using common memory bus to transfer restart data from non-faulty processor to failed processor |
JPS62197858A (ja) * | 1986-02-26 | 1987-09-01 | Hitachi Ltd | システム間デ−タベ−ス共用方式 |
US4967347A (en) * | 1986-04-03 | 1990-10-30 | Bh-F (Triplex) Inc. | Multiple-redundant fault detection system and related method for its use |
KR890001847B1 (ko) * | 1986-05-07 | 1989-05-25 | 삼성전자 주식회사 | 반도체 메모리 장치의 리던던시 회로 |
US4872166A (en) * | 1986-09-10 | 1989-10-03 | Nec Corporation | Information processing system capable of reducing invalid memory operations by detecting an error in a main memory |
US4807228A (en) * | 1987-03-18 | 1989-02-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of spare capacity use for fault detection in a multiprocessor system |
US4958273A (en) * | 1987-08-26 | 1990-09-18 | International Business Machines Corporation | Multiprocessor system architecture with high availability |
JPH07111713B2 (ja) * | 1988-02-24 | 1995-11-29 | 富士通株式会社 | 構成変更制御方式 |
JP2561696B2 (ja) * | 1988-03-31 | 1996-12-11 | 三菱電機株式会社 | ネットワークシステムにおける共用領域管理方法 |
US4965717A (en) * | 1988-12-09 | 1990-10-23 | Tandem Computers Incorporated | Multiple processor system having shared memory with private-write capability |
US5134616A (en) * | 1990-02-13 | 1992-07-28 | International Business Machines Corporation | Dynamic ram with on-chip ecc and optimized bit and word redundancy |
-
1991
- 1991-05-15 EP EP91107879A patent/EP0457308B1/de not_active Expired - Lifetime
- 1991-05-15 DE DE69124285T patent/DE69124285T2/de not_active Expired - Fee Related
-
1994
- 1994-05-24 US US08/249,046 patent/US5548743A/en not_active Expired - Lifetime
-
1995
- 1995-04-28 US US08/430,315 patent/US5568609A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0457308A3 (en) | 1992-11-04 |
EP0457308B1 (de) | 1997-01-22 |
EP0457308A2 (de) | 1991-11-21 |
US5548743A (en) | 1996-08-20 |
US5568609A (en) | 1996-10-22 |
DE69124285T2 (de) | 1997-08-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |