DE69123063D1 - Gleichstromversorgte integrierte Schaltung vom Josephson-Typ - Google Patents
Gleichstromversorgte integrierte Schaltung vom Josephson-TypInfo
- Publication number
- DE69123063D1 DE69123063D1 DE69123063T DE69123063T DE69123063D1 DE 69123063 D1 DE69123063 D1 DE 69123063D1 DE 69123063 T DE69123063 T DE 69123063T DE 69123063 T DE69123063 T DE 69123063T DE 69123063 D1 DE69123063 D1 DE 69123063D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- powered integrated
- josephson
- type
- josephson type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
- H03K19/1952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with electro-magnetic coupling of the control current
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/381—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using cryogenic components, e.g. Josephson gates
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/38—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of superconductive devices
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S505/00—Superconductor technology: apparatus, material, process
- Y10S505/825—Apparatus per se, device per se, or process of making or operating same
- Y10S505/856—Electrical transmission or interconnection system
- Y10S505/857—Nonlinear solid-state device system or circuit
- Y10S505/86—Gating, i.e. switching circuit
- Y10S505/861—Gating, i.e. switching circuit with josephson junction
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S505/00—Superconductor technology: apparatus, material, process
- Y10S505/825—Apparatus per se, device per se, or process of making or operating same
- Y10S505/856—Electrical transmission or interconnection system
- Y10S505/857—Nonlinear solid-state device system or circuit
- Y10S505/865—Nonlinear solid-state device system or circuit with josephson junction
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Hardware Design (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2028550A JP2550198B2 (ja) | 1990-02-09 | 1990-02-09 | 直流電源駆動ジョセフソン集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69123063D1 true DE69123063D1 (de) | 1996-12-19 |
DE69123063T2 DE69123063T2 (de) | 1997-05-22 |
Family
ID=12251765
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69123063T Expired - Fee Related DE69123063T2 (de) | 1990-02-09 | 1991-02-07 | Gleichstromversorgte integrierte Schaltung vom Josephson-Typ |
Country Status (4)
Country | Link |
---|---|
US (1) | US5124583A (de) |
EP (1) | EP0441634B1 (de) |
JP (1) | JP2550198B2 (de) |
DE (1) | DE69123063T2 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5646526A (en) * | 1993-12-20 | 1997-07-08 | Hitachi, Ltd. | Josephson signal detector, measurement device using the same, and method of use |
US7129870B2 (en) * | 2003-08-29 | 2006-10-31 | Fujitsu Limited | Superconducting latch driver circuit generating sufficient output voltage and pulse-width |
US7615385B2 (en) | 2006-09-20 | 2009-11-10 | Hypres, Inc | Double-masking technique for increasing fabrication yield in superconducting electronics |
US8571614B1 (en) | 2009-10-12 | 2013-10-29 | Hypres, Inc. | Low-power biasing networks for superconducting integrated circuits |
US9021000B2 (en) | 2012-06-29 | 2015-04-28 | International Business Machines Corporation | High speed and low power circuit structure for barrel shifter |
US10222416B1 (en) | 2015-04-14 | 2019-03-05 | Hypres, Inc. | System and method for array diagnostics in superconducting integrated circuit |
US10411713B2 (en) | 2017-02-04 | 2019-09-10 | Microsoft Technology Licensing, Llc | Superconducting circuits based devices and methods |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH559481A5 (de) * | 1973-12-13 | 1975-02-28 | Ibm | |
US4373138A (en) * | 1978-12-29 | 1983-02-08 | Bell Telephone Laboratories, Incorporated | Hybrid unlatching flip-flop logic element |
JPS57203318A (en) * | 1981-06-10 | 1982-12-13 | Hitachi Ltd | Superconductive digital circuit |
JPS6029407A (ja) * | 1983-07-27 | 1985-02-14 | Tohoku Metal Ind Ltd | 合金の製造方法 |
-
1990
- 1990-02-09 JP JP2028550A patent/JP2550198B2/ja not_active Expired - Fee Related
-
1991
- 1991-02-05 US US07/650,933 patent/US5124583A/en not_active Expired - Lifetime
- 1991-02-07 DE DE69123063T patent/DE69123063T2/de not_active Expired - Fee Related
- 1991-02-07 EP EP91301016A patent/EP0441634B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5124583A (en) | 1992-06-23 |
EP0441634A3 (en) | 1992-04-08 |
JPH03235419A (ja) | 1991-10-21 |
EP0441634B1 (de) | 1996-11-13 |
JP2550198B2 (ja) | 1996-11-06 |
EP0441634A2 (de) | 1991-08-14 |
DE69123063T2 (de) | 1997-05-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: HITACHI, LTD., TOKIO/TOKYO, JP NEW ENERGY AND INDU |
|
8339 | Ceased/non-payment of the annual fee |