DE69119446D1 - Dekodierschaltung - Google Patents

Dekodierschaltung

Info

Publication number
DE69119446D1
DE69119446D1 DE69119446T DE69119446T DE69119446D1 DE 69119446 D1 DE69119446 D1 DE 69119446D1 DE 69119446 T DE69119446 T DE 69119446T DE 69119446 T DE69119446 T DE 69119446T DE 69119446 D1 DE69119446 D1 DE 69119446D1
Authority
DE
Germany
Prior art keywords
decoding circuit
decoding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69119446T
Other languages
English (en)
Other versions
DE69119446T2 (de
Inventor
Tatsunori Murotani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69119446D1 publication Critical patent/DE69119446D1/de
Application granted granted Critical
Publication of DE69119446T2 publication Critical patent/DE69119446T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
DE69119446T 1990-02-26 1991-02-26 Dekodierschaltung Expired - Fee Related DE69119446T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4506690 1990-02-26

Publications (2)

Publication Number Publication Date
DE69119446D1 true DE69119446D1 (de) 1996-06-20
DE69119446T2 DE69119446T2 (de) 1996-10-31

Family

ID=12708979

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69119446T Expired - Fee Related DE69119446T2 (de) 1990-02-26 1991-02-26 Dekodierschaltung

Country Status (4)

Country Link
US (1) US5159215A (de)
EP (1) EP0444602B1 (de)
KR (1) KR940005515B1 (de)
DE (1) DE69119446T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
GB9007791D0 (en) 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
JP2977321B2 (ja) * 1991-05-20 1999-11-15 株式会社東芝 マルチプレクサ
US5255224A (en) * 1991-12-18 1993-10-19 International Business Machines Corporation Boosted drive system for master/local word line memory architecture
US5327026A (en) * 1993-02-17 1994-07-05 United Memories, Inc. Self-timed bootstrap decoder
JP2591907B2 (ja) * 1994-05-24 1997-03-19 日本電気アイシーマイコンシステム株式会社 読み出し専用半導体記憶装置のデコード回路
JP4198201B2 (ja) * 1995-06-02 2008-12-17 株式会社ルネサステクノロジ 半導体装置
JPH1116365A (ja) * 1997-06-20 1999-01-22 Oki Micro Design Miyazaki:Kk アドレスデコーダおよび半導体記憶装置、並びに半導体装置
US6137318A (en) * 1997-12-09 2000-10-24 Oki Electric Industry Co., Ltd. Logic circuit having dummy MOS transistor
US7230453B2 (en) * 2003-12-29 2007-06-12 Stmicroelectronics Pvt. Ltd. Output buffer providing multiple voltages

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472691A (en) * 1977-11-21 1979-06-11 Toshiba Corp Semiconductor device
US4618784A (en) * 1985-01-28 1986-10-21 International Business Machines Corporation High-performance, high-density CMOS decoder/driver circuit
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type
JPS6238591A (ja) * 1985-08-14 1987-02-19 Fujitsu Ltd 相補型の半導体メモリ装置
US4760560A (en) * 1985-08-30 1988-07-26 Kabushiki Kaisha Toshiba Random access memory with resistance to crystal lattice memory errors
JPS62229870A (ja) * 1986-01-22 1987-10-08 Mitsubishi Electric Corp 半導体集積回路
EP0300184B1 (de) * 1987-06-10 1992-08-26 Siemens Aktiengesellschaft Schaltungsanordnung in einer integrierten Halbleiterschaltung
US4918663A (en) * 1987-09-16 1990-04-17 Motorola, Inc. Latch-up control for a CMOS memory with a pumped well
US4843261A (en) * 1988-02-29 1989-06-27 International Business Machines Corporation Complementary output, high-density CMOS decoder/driver circuit for semiconductor memories
JP2547615B2 (ja) * 1988-06-16 1996-10-23 三菱電機株式会社 読出専用半導体記憶装置および半導体記憶装置

Also Published As

Publication number Publication date
EP0444602A3 (en) 1992-07-15
DE69119446T2 (de) 1996-10-31
KR940005515B1 (ko) 1994-06-20
EP0444602B1 (de) 1996-05-15
EP0444602A2 (de) 1991-09-04
KR920000182A (ko) 1992-01-10
US5159215A (en) 1992-10-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee