DE69029779D1 - Halbleiteranordnung und verfahren zur herstellung derselben - Google Patents

Halbleiteranordnung und verfahren zur herstellung derselben

Info

Publication number
DE69029779D1
DE69029779D1 DE69029779T DE69029779T DE69029779D1 DE 69029779 D1 DE69029779 D1 DE 69029779D1 DE 69029779 T DE69029779 T DE 69029779T DE 69029779 T DE69029779 T DE 69029779T DE 69029779 D1 DE69029779 D1 DE 69029779D1
Authority
DE
Germany
Prior art keywords
producing
same
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029779T
Other languages
English (en)
Other versions
DE69029779T2 (de
Inventor
Katsujiro Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE69029779D1 publication Critical patent/DE69029779D1/de
Publication of DE69029779T2 publication Critical patent/DE69029779T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69029779T 1989-04-25 1990-04-23 Halbleiteranordnung und verfahren zur herstellung derselben Expired - Fee Related DE69029779T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10495789 1989-04-25
PCT/JP1990/000523 WO1990013145A1 (en) 1989-04-25 1990-04-23 Semiconductor device and method of producing the same

Publications (2)

Publication Number Publication Date
DE69029779D1 true DE69029779D1 (de) 1997-03-06
DE69029779T2 DE69029779T2 (de) 1997-09-18

Family

ID=14394577

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029779T Expired - Fee Related DE69029779T2 (de) 1989-04-25 1990-04-23 Halbleiteranordnung und verfahren zur herstellung derselben

Country Status (4)

Country Link
EP (1) EP0422250B1 (de)
JP (1) JPH0368165A (de)
DE (1) DE69029779T2 (de)
WO (1) WO1990013145A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2340999A (en) 1998-08-28 2000-03-01 Ericsson Telefon Ab L M Isolating MOS transistors from substrates
US7598573B2 (en) 2004-11-16 2009-10-06 Robert Paul Masleid Systems and methods for voltage distribution via multiple epitaxial layers
US7667288B2 (en) * 2004-11-16 2010-02-23 Masleid Robert P Systems and methods for voltage distribution via epitaxial layers
JP4810904B2 (ja) 2005-07-20 2011-11-09 ソニー株式会社 高周波スイッチ回路を有する高周波装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310119U (de) * 1976-07-09 1978-01-27
JPS60223157A (ja) * 1984-04-19 1985-11-07 Nippon Denso Co Ltd 半導体装置
JPS61273580A (ja) * 1985-05-29 1986-12-03 株式会社東芝 表示装置における画面区分化方式
JPS6272839A (ja) * 1985-09-24 1987-04-03 清水建設株式会社 充填鋼管コンクリート柱の構造
JPS62276868A (ja) * 1986-05-26 1987-12-01 Hitachi Ltd 半導体集積回路装置
JPS6490349A (en) * 1987-09-30 1989-04-06 Takenaka Komuten Co Square steel pipe/concrete pillar
JPH01147854A (ja) * 1987-12-04 1989-06-09 Nissan Motor Co Ltd 半導体装置
JPH02243847A (ja) * 1989-03-17 1990-09-27 Nakajima Kokan Kk 耐火耐熱型構造材

Also Published As

Publication number Publication date
EP0422250A4 (en) 1993-01-27
JPH0368165A (ja) 1991-03-25
EP0422250A1 (de) 1991-04-17
WO1990013145A1 (en) 1990-11-01
DE69029779T2 (de) 1997-09-18
EP0422250B1 (de) 1997-01-22

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication related to discontinuation of the patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee