DE69029173D1 - Mikroprozessor - Google Patents

Mikroprozessor

Info

Publication number
DE69029173D1
DE69029173D1 DE69029173T DE69029173T DE69029173D1 DE 69029173 D1 DE69029173 D1 DE 69029173D1 DE 69029173 T DE69029173 T DE 69029173T DE 69029173 T DE69029173 T DE 69029173T DE 69029173 D1 DE69029173 D1 DE 69029173D1
Authority
DE
Germany
Prior art keywords
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029173T
Other languages
English (en)
Other versions
DE69029173T2 (de
Inventor
Harutaka Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69029173D1 publication Critical patent/DE69029173D1/de
Publication of DE69029173T2 publication Critical patent/DE69029173T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
DE69029173T 1989-07-13 1990-07-13 Mikroprozessor Expired - Fee Related DE69029173T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17906689 1989-07-13

Publications (2)

Publication Number Publication Date
DE69029173D1 true DE69029173D1 (de) 1997-01-02
DE69029173T2 DE69029173T2 (de) 1997-04-10

Family

ID=16059509

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69029173T Expired - Fee Related DE69029173T2 (de) 1989-07-13 1990-07-13 Mikroprozessor

Country Status (5)

Country Link
US (1) US5379394A (de)
EP (1) EP0408058B1 (de)
JP (1) JPH0711793B2 (de)
KR (1) KR920008427B1 (de)
DE (1) DE69029173T2 (de)

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US6336180B1 (en) 1997-04-30 2002-01-01 Canon Kabushiki Kaisha Method, apparatus and system for managing virtual memory with virtual-physical mapping
US6006302A (en) * 1990-06-04 1999-12-21 Hitachi, Ltd. Multiple bus system using a data transfer unit
DE69231957T2 (de) * 1991-10-21 2002-04-04 Toshiba Kawasaki Kk Hochgeschwindigkeitsprozessor zum fähiger Abhandeln mehrerer Unterbrechungen
KR100294105B1 (ko) * 1992-04-29 2001-09-17 썬 마이크로시스템즈, 인코포레이티드 멀티 프로세서 컴퓨터 시스템의 일관성 카피-백 버퍼용 방법 및 장치
JP3619532B2 (ja) * 1993-11-08 2005-02-09 株式会社ルネサステクノロジ 半導体集積回路装置
US5557743A (en) * 1994-04-05 1996-09-17 Motorola, Inc. Protection circuit for a microprocessor
US5822550A (en) * 1994-12-22 1998-10-13 Texas Instruments Incorporated Split data path fast at-bus on chip circuits systems and methods
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
FR2736482B1 (fr) * 1995-07-07 1997-09-12 Sextant Avionique Dispositif de communication entre une pluralite de modules fonctionnels installes dans une unite locale et un bus externe de type arinc 629
JP2976850B2 (ja) * 1995-07-13 1999-11-10 日本電気株式会社 データ処理装置
JP4312272B2 (ja) * 1995-10-06 2009-08-12 モトローラ・インコーポレイテッド 内部メモリへのアクセスを制限するマイクロコントローラ
JP3655403B2 (ja) 1995-10-09 2005-06-02 株式会社ルネサステクノロジ データ処理装置
US5890011A (en) * 1997-01-27 1999-03-30 International Business Machines Corporation Method and system for dynamically translating bus addresses within a computer system
AUPO648397A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Improvements in multiprocessor architecture operation
JP3790323B2 (ja) * 1997-04-16 2006-06-28 株式会社ルネサステクノロジ データ転送制御装置、マイクロコンピュータ及びデータ処理システム
AUPO647997A0 (en) * 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6707463B1 (en) 1997-04-30 2004-03-16 Canon Kabushiki Kaisha Data normalization technique
US6414687B1 (en) 1997-04-30 2002-07-02 Canon Kabushiki Kaisha Register setting-micro programming system
US6674536B2 (en) 1997-04-30 2004-01-06 Canon Kabushiki Kaisha Multi-instruction stream processor
US6289138B1 (en) 1997-04-30 2001-09-11 Canon Kabushiki Kaisha General image processor
US6246396B1 (en) 1997-04-30 2001-06-12 Canon Kabushiki Kaisha Cached color conversion method and apparatus
JP2000021193A (ja) * 1998-07-01 2000-01-21 Fujitsu Ltd メモリ試験方法及び装置並びに記憶媒体
US6618777B1 (en) 1999-01-21 2003-09-09 Analog Devices, Inc. Method and apparatus for communicating between multiple functional units in a computer environment
US6701432B1 (en) * 1999-04-01 2004-03-02 Netscreen Technologies, Inc. Firewall including local bus
US6457100B1 (en) 1999-09-15 2002-09-24 International Business Machines Corporation Scaleable shared-memory multi-processor computer system having repetitive chip structure with efficient busing and coherence controls
JP3940539B2 (ja) * 2000-02-03 2007-07-04 株式会社日立製作所 半導体集積回路
US7269704B2 (en) * 2005-03-30 2007-09-11 Atmel Corporation Method and apparatus for reducing system inactivity during time data float delay and external memory write
FR2884629B1 (fr) * 2005-04-15 2007-06-22 Atmel Corp Dispositif d'amelioration de la bande passante pour des circuits munis de controleurs memoires multiples
US7836258B2 (en) * 2006-11-13 2010-11-16 International Business Machines Corporation Dynamic data cache invalidate with data dependent expiration

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4467414A (en) * 1980-08-22 1984-08-21 Nippon Electric Co., Ltd. Cashe memory arrangement comprising a cashe buffer in combination with a pair of cache memories
US4488256A (en) * 1981-11-23 1984-12-11 Motorola, Inc. Memory management unit having means for detecting and preventing mapping conflicts
US5097413A (en) * 1983-09-20 1992-03-17 Mensch Jr William D Abort circuitry for microprocessor
US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller
IT1175678B (it) * 1984-08-31 1987-07-15 Mangnaghi Oleodinamica Spa Gruppo servoattuatore ridondante particolarmente per l'azionamento di organi di controllo di volo in velivoli
CA1269176A (en) * 1985-02-22 1990-05-15 Fairchild Camera And Instrument Corporation Multiple bus system including a microprocessor having separate instruction and data interfaces and caches
US4916603A (en) * 1985-03-18 1990-04-10 Wang Labortatories, Inc. Distributed reference and change table for a virtual memory system
US4953073A (en) * 1986-02-06 1990-08-28 Mips Computer Systems, Inc. Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US4837739A (en) * 1986-07-25 1989-06-06 Ford Aerospace & Communications Corporation Telemetry data processor
GB2200483B (en) * 1987-01-22 1991-10-16 Nat Semiconductor Corp Memory referencing in a high performance microprocessor
DE3740834A1 (de) * 1987-01-22 1988-08-04 Nat Semiconductor Corp Aufrechterhaltung der kohaerenz zwischen einem mikroprozessorenintegrierten cache-speicher und einem externen speicher
US5163133A (en) * 1987-02-17 1992-11-10 Sam Technology, Inc. Parallel processing system having a broadcast, result, and instruction bus for transmitting, receiving and controlling the computation of data
US4912636A (en) * 1987-03-13 1990-03-27 Magar Surendar S Data processing device with multiple on chip memory buses
US5073969A (en) * 1988-08-01 1991-12-17 Intel Corporation Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal
JPH02122346A (ja) * 1988-11-01 1990-05-10 Fujitsu Ltd キャッシュメモリ制御方式
US5117350A (en) * 1988-12-15 1992-05-26 Flashpoint Computer Corporation Memory address mechanism in a distributed memory architecture
US5067078A (en) * 1989-04-17 1991-11-19 Motorola, Inc. Cache which provides status information

Also Published As

Publication number Publication date
EP0408058A2 (de) 1991-01-16
US5379394A (en) 1995-01-03
DE69029173T2 (de) 1997-04-10
EP0408058A3 (en) 1992-09-02
JPH03135641A (ja) 1991-06-10
JPH0711793B2 (ja) 1995-02-08
KR910003498A (ko) 1991-02-27
KR920008427B1 (ko) 1992-09-28
EP0408058B1 (de) 1996-11-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee