DE69028607D1 - Mikroprozessor mit internem Cache-Speicher - Google Patents

Mikroprozessor mit internem Cache-Speicher

Info

Publication number
DE69028607D1
DE69028607D1 DE69028607T DE69028607T DE69028607D1 DE 69028607 D1 DE69028607 D1 DE 69028607D1 DE 69028607 T DE69028607 T DE 69028607T DE 69028607 T DE69028607 T DE 69028607T DE 69028607 D1 DE69028607 D1 DE 69028607D1
Authority
DE
Germany
Prior art keywords
microprocessor
cache memory
internal cache
internal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69028607T
Other languages
English (en)
Other versions
DE69028607T2 (de
Inventor
Yoshikuni Sato
Kouji Maemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69028607D1 publication Critical patent/DE69028607D1/de
Application granted granted Critical
Publication of DE69028607T2 publication Critical patent/DE69028607T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Microcomputers (AREA)
DE1990628607 1989-12-15 1990-12-17 Mikroprozessor mit internem Cache-Speicher Expired - Fee Related DE69028607T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1326918A JPH03186981A (ja) 1989-12-15 1989-12-15 キャッシュメモリ内蔵マイクロプロセッサ

Publications (2)

Publication Number Publication Date
DE69028607D1 true DE69028607D1 (de) 1996-10-24
DE69028607T2 DE69028607T2 (de) 1997-04-17

Family

ID=18193212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1990628607 Expired - Fee Related DE69028607T2 (de) 1989-12-15 1990-12-17 Mikroprozessor mit internem Cache-Speicher

Country Status (4)

Country Link
EP (1) EP0432807B1 (de)
JP (1) JPH03186981A (de)
KR (1) KR930004431B1 (de)
DE (1) DE69028607T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993011488A1 (en) * 1991-12-06 1993-06-10 Seiko Epson Corporation A rom with ram cell and cyclic redundancy check circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651321A (en) * 1983-08-29 1987-03-17 Amdahl Corporation Apparatus for reducing storage necessary for error correction and detection in data processing machines
US4794524A (en) * 1984-07-03 1988-12-27 Zilog, Inc. Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
US4851993A (en) * 1987-04-20 1989-07-25 Amdahl Corporation Cache move-in bypass

Also Published As

Publication number Publication date
KR930004431B1 (en) 1993-05-27
EP0432807A3 (en) 1991-10-16
JPH03186981A (ja) 1991-08-14
EP0432807A2 (de) 1991-06-19
EP0432807B1 (de) 1996-09-18
KR910012931A (ko) 1991-08-08
DE69028607T2 (de) 1997-04-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee