DE69023219D1 - Mit verschiedenen Modulatoren versehener Teiler mit gebrochenem Teilverhältnis. - Google Patents

Mit verschiedenen Modulatoren versehener Teiler mit gebrochenem Teilverhältnis.

Info

Publication number
DE69023219D1
DE69023219D1 DE69023219T DE69023219T DE69023219D1 DE 69023219 D1 DE69023219 D1 DE 69023219D1 DE 69023219 T DE69023219 T DE 69023219T DE 69023219 T DE69023219 T DE 69023219T DE 69023219 D1 DE69023219 D1 DE 69023219D1
Authority
DE
Germany
Prior art keywords
part ratio
broken part
different modulators
divider provided
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69023219T
Other languages
English (en)
Other versions
DE69023219T2 (de
Inventor
Brian M Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE69023219D1 publication Critical patent/DE69023219D1/de
Application granted granted Critical
Publication of DE69023219T2 publication Critical patent/DE69023219T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/02—Amplitude modulation, i.e. PAM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
DE69023219T 1990-01-23 1990-11-27 Mit verschiedenen Modulatoren versehener Teiler mit gebrochenem Teilverhältnis. Expired - Fee Related DE69023219T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US46965690A 1990-01-23 1990-01-23

Publications (2)

Publication Number Publication Date
DE69023219D1 true DE69023219D1 (de) 1995-11-30
DE69023219T2 DE69023219T2 (de) 1996-04-04

Family

ID=23864594

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69023219T Expired - Fee Related DE69023219T2 (de) 1990-01-23 1990-11-27 Mit verschiedenen Modulatoren versehener Teiler mit gebrochenem Teilverhältnis.

Country Status (5)

Country Link
EP (1) EP0438867B1 (de)
JP (1) JPH04212522A (de)
KR (1) KR910015116A (de)
CA (1) CA2019297A1 (de)
DE (1) DE69023219T2 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055802A (en) * 1990-04-30 1991-10-08 Motorola, Inc. Multiaccumulator sigma-delta fractional-n synthesis
US5166642A (en) * 1992-02-18 1992-11-24 Motorola, Inc. Multiple accumulator fractional N synthesis with series recombination
US5625358A (en) * 1993-09-13 1997-04-29 Analog Devices, Inc. Digital phase-locked loop utilizing a high order sigma-delta modulator
US5495206A (en) * 1993-10-29 1996-02-27 Motorola, Inc. Fractional N frequency synthesis with residual error correction and method thereof
WO1997006600A1 (fr) * 1995-08-03 1997-02-20 Anritsu Corporation Diviseur rationnel de frequences et synthetiseur de frequences employant ce diviseur de frequences
US5684795A (en) * 1996-01-30 1997-11-04 Motorola, Inc. Method and apparatus for controlling a fractional-N synthesizer in a time division multiple access system
US6047029A (en) * 1997-09-16 2000-04-04 Telefonaktiebolaget Lm Ericsson Post-filtered delta sigma for controlling a phase locked loop modulator
US6011815A (en) * 1997-09-16 2000-01-04 Telefonaktiebolaget Lm Ericsson Compensated ΔΣ controlled phase locked loop modulator
GB2335322B (en) * 1998-03-13 2002-04-24 Ericsson Telefon Ab L M Phase detector
JP2002016494A (ja) 2000-06-28 2002-01-18 Ando Electric Co Ltd 位相同期ループ回路
US6941330B2 (en) 2000-09-27 2005-09-06 Hughes Electronics Corporation Feed forward sigma delta interpolator for use in a fractional-N synthesizer
JP4493887B2 (ja) * 2001-08-03 2010-06-30 セイコーＮｐｃ株式会社 フラクショナルｎ周波数シンセサイザ及びその動作方法
WO2005015744A1 (en) * 2003-07-25 2005-02-17 Fujitsu Limited Variable frequency synthesizer comprising a sigma-delta modulator
US7482885B2 (en) 2005-12-29 2009-01-27 Orca Systems, Inc. Method of frequency synthesis for fast switching
US7519349B2 (en) 2006-02-17 2009-04-14 Orca Systems, Inc. Transceiver development in VHF/UHF/GSM/GPS/bluetooth/cordless telephones

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2140232B (en) * 1983-05-17 1986-10-29 Marconi Instruments Ltd Frequency synthesisers
JPS62502232A (ja) * 1985-02-21 1987-08-27 シーメンス　プレッシー　エレクトロニック　システムズ　リミテッド 周波数合成器またはそれに関する改良
JP2543095B2 (ja) * 1987-09-14 1996-10-16 松下電器産業株式会社 オ―バ―サンプリング型ｄ／ａ変換器
JPH01204528A (ja) * 1988-02-10 1989-08-17 Fujitsu Ltd Ａ／ｄ変換器

Also Published As

Publication number Publication date
EP0438867A2 (de) 1991-07-31
EP0438867B1 (de) 1995-10-25
KR910015116A (ko) 1991-08-31
EP0438867A3 (en) 1991-10-02
JPH04212522A (ja) 1992-08-04
CA2019297A1 (en) 1991-07-23
DE69023219T2 (de) 1996-04-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D. STAATES, US

8339 Ceased/non-payment of the annual fee