DE68927255D1 - Impulsgeneratorschaltung - Google Patents

Impulsgeneratorschaltung

Info

Publication number
DE68927255D1
DE68927255D1 DE68927255T DE68927255T DE68927255D1 DE 68927255 D1 DE68927255 D1 DE 68927255D1 DE 68927255 T DE68927255 T DE 68927255T DE 68927255 T DE68927255 T DE 68927255T DE 68927255 D1 DE68927255 D1 DE 68927255D1
Authority
DE
Germany
Prior art keywords
pulse generator
generator circuit
circuit
pulse
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927255T
Other languages
English (en)
Other versions
DE68927255T2 (de
Inventor
Thomas James C O Intern Davies
Leonardus Chritien M Pfennings
Peter Hermann C O Interna Voss
Cormac Michael C O I O'connell
Cathal Gerard C O Inter Phelan
Hans C O International Ontrop
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Application granted granted Critical
Publication of DE68927255D1 publication Critical patent/DE68927255D1/de
Publication of DE68927255T2 publication Critical patent/DE68927255T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/033—Monostable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
DE68927255T 1988-12-14 1989-12-08 Impulsgeneratorschaltung Expired - Fee Related DE68927255T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8829154A GB2226725A (en) 1988-12-14 1988-12-14 Pulse generator circuit arrangement

Publications (2)

Publication Number Publication Date
DE68927255D1 true DE68927255D1 (de) 1996-10-31
DE68927255T2 DE68927255T2 (de) 1997-03-27

Family

ID=10648461

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927255T Expired - Fee Related DE68927255T2 (de) 1988-12-14 1989-12-08 Impulsgeneratorschaltung

Country Status (6)

Country Link
US (1) US5265064A (de)
EP (1) EP0373703B1 (de)
JP (1) JPH02193408A (de)
KR (1) KR900011141A (de)
DE (1) DE68927255T2 (de)
GB (1) GB2226725A (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498989A (en) * 1994-04-19 1996-03-12 Xilinx, Inc. Integrated circuit one shot with extended length output pulse
US5488319A (en) * 1994-08-18 1996-01-30 International Business Machines Corporation Latch interface for self-reset logic
US5563843A (en) * 1995-03-09 1996-10-08 Intel Corporation Method and circuitry for preventing propagation of undesired ATD pulses in a flash memory device
US5517137A (en) * 1995-05-19 1996-05-14 Alliance Semiconductor Corporation Synchronous self-timed clock pulse circuit having improved power-up performance
US5541537A (en) * 1995-06-02 1996-07-30 International Business Machines Corporation High speed static circuit design
IT1305118B1 (it) * 1998-10-06 2001-04-10 St Microelectronics Srl Circuito di rilevamento di transizioni di indirizzo in memorie asemiconduttore.

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1372183A (en) * 1970-08-03 1974-10-30 Aei Telecommunications Canada Digital impulse corrector
JPS5963094A (ja) * 1982-10-04 1984-04-10 Fujitsu Ltd メモリ装置
JPS6154098A (ja) * 1984-08-23 1986-03-18 Fujitsu Ltd パルス発生回路
US4751680A (en) * 1986-03-03 1988-06-14 Motorola, Inc. Bit line equalization in a memory
JPH06101227B2 (ja) * 1986-11-29 1994-12-12 三菱電機株式会社 半導体メモリ装置
US4947374A (en) * 1987-05-12 1990-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memeory device in which writing is inhibited in address skew period and controlling method thereof

Also Published As

Publication number Publication date
KR900011141A (ko) 1990-07-11
GB2226725A (en) 1990-07-04
GB8829154D0 (en) 1989-01-25
US5265064A (en) 1993-11-23
DE68927255T2 (de) 1997-03-27
JPH02193408A (ja) 1990-07-31
EP0373703A2 (de) 1990-06-20
EP0373703B1 (de) 1996-09-25
EP0373703A3 (de) 1990-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8339 Ceased/non-payment of the annual fee