DE68925615D1 - Digitalrechnersystem mit Niederstromverbrauchmodus - Google Patents

Digitalrechnersystem mit Niederstromverbrauchmodus

Info

Publication number
DE68925615D1
DE68925615D1 DE68925615T DE68925615T DE68925615D1 DE 68925615 D1 DE68925615 D1 DE 68925615D1 DE 68925615 T DE68925615 T DE 68925615T DE 68925615 T DE68925615 T DE 68925615T DE 68925615 D1 DE68925615 D1 DE 68925615D1
Authority
DE
Germany
Prior art keywords
computer system
power consumption
low power
digital computer
consumption mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68925615T
Other languages
English (en)
Other versions
DE68925615T2 (de
Inventor
Antone Louis Fourcroy
Mark William Mcdermott
John P Dunn
Bradley G Burgess
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE68925615D1 publication Critical patent/DE68925615D1/de
Application granted granted Critical
Publication of DE68925615T2 publication Critical patent/DE68925615T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
DE68925615T 1988-11-10 1989-11-02 Digitalrechnersystem mit Niederstromverbrauchmodus Expired - Fee Related DE68925615T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26934488A 1988-11-10 1988-11-10

Publications (2)

Publication Number Publication Date
DE68925615D1 true DE68925615D1 (de) 1996-03-21
DE68925615T2 DE68925615T2 (de) 1996-09-12

Family

ID=23026857

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68925615T Expired - Fee Related DE68925615T2 (de) 1988-11-10 1989-11-02 Digitalrechnersystem mit Niederstromverbrauchmodus

Country Status (5)

Country Link
US (1) US5361392A (de)
EP (1) EP0368144B1 (de)
JP (1) JP2782367B2 (de)
KR (1) KR0147063B1 (de)
DE (1) DE68925615T2 (de)

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US5842029A (en) * 1991-10-17 1998-11-24 Intel Corporation Method and apparatus for powering down an integrated circuit transparently and its phase locked loop
GB2264794B (en) * 1992-03-06 1995-09-20 Intel Corp Method and apparatus for automatic power management in a high integration floppy disk controller
US6343363B1 (en) 1994-09-22 2002-01-29 National Semiconductor Corporation Method of invoking a low power mode in a computer system using a halt instruction
US5630143A (en) * 1992-03-27 1997-05-13 Cyrix Corporation Microprocessor with externally controllable power management
JP3529805B2 (ja) * 1992-03-27 2004-05-24 ナショナル・セミコンダクター・コーポレイション ハードウェア制御パワー管理機能と選択可能な入出力制御ピンとを有するマイクロプロセッサ
US5613135A (en) * 1992-09-17 1997-03-18 Kabushiki Kaisha Toshiba Portable computer having dedicated register group and peripheral controller bus between system bus and peripheral controller
US5473767A (en) * 1992-11-03 1995-12-05 Intel Corporation Method and apparatus for asynchronously stopping the clock in a processor
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5586332A (en) * 1993-03-24 1996-12-17 Intel Corporation Power management for low power processors through the use of auto clock-throttling
US5548763A (en) * 1993-07-26 1996-08-20 International Business Machines Corporation Desk top computer system having multi-level power management
US5894577A (en) * 1993-09-22 1999-04-13 Advanced Micro Devices, Inc. Interrupt controller with external in-service indication for power management within a computer system
US5471625A (en) * 1993-09-27 1995-11-28 Motorola, Inc. Method and apparatus for entering a low-power mode and controlling an external bus of a data processing system during low-power mode
KR100352045B1 (ko) * 1994-01-10 2002-12-28 선 마이크로시스템즈 인코퍼레이티드 컴퓨터시스템에서전력소모를감소시키기위한방법및장치
EP0666525B1 (de) * 1994-02-04 2001-09-12 Intel Corporation Verfahren und Vorrichtung zur Stromverbrauchssteuerung in einem Rechnersystem
ATE231254T1 (de) * 1994-04-28 2003-02-15 Advanced Micro Devices Inc System zur steuerung eines peripheriebustaktsignals
KR960012838B1 (ko) * 1994-06-20 1996-09-24 삼성전자 주식회사 스톱 클럭 제어장치와 그 방법
US5752011A (en) * 1994-06-20 1998-05-12 Thomas; C. Douglas Method and system for controlling a processor's clock frequency in accordance with the processor's temperature
US5933649A (en) * 1994-06-20 1999-08-03 Samsung Electronics Co., Ltd. Method and device for controlling a CPU stop clock interrupt
US5708816A (en) * 1994-09-30 1998-01-13 Apple Computer, Inc. Method and apparatus for interrupt management for low power PDA
JP3846939B2 (ja) * 1995-08-30 2006-11-15 フリースケール セミコンダクター インコーポレイテッド データプロセッサ
US5713029A (en) * 1995-09-29 1998-01-27 International Business Machines Corporation Information handling system including doze mode control
US5842028A (en) * 1995-10-16 1998-11-24 Texas Instruments Incorporated Method for waking up an integrated circuit from low power mode
US5740410A (en) * 1995-12-15 1998-04-14 Cyrix Corporation Static clock generator
US5815693A (en) * 1995-12-15 1998-09-29 National Semiconductor Corporation Processor having a frequency modulated core clock based on the criticality of program activity
US5815692A (en) * 1995-12-15 1998-09-29 National Semiconductor Corporation Distributed clock generator
US5802132A (en) 1995-12-29 1998-09-01 Intel Corporation Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5821784A (en) * 1995-12-29 1998-10-13 Intel Corporation Method and apparatus for generating 2/N mode bus clock signals
US5834956A (en) 1995-12-29 1998-11-10 Intel Corporation Core clock correction in a 2/N mode clocking scheme
JPH1091443A (ja) * 1996-05-22 1998-04-10 Seiko Epson Corp 情報処理回路、マイクロコンピュータ及び電子機器
KR100378864B1 (ko) * 1996-07-15 2003-05-17 칼소닉 칸세이 가부시끼가이샤 마이크로컴퓨터장치
US5826067A (en) * 1996-09-06 1998-10-20 Intel Corporation Method and apparatus for preventing logic glitches in a 2/n clocking scheme
US5862373A (en) * 1996-09-06 1999-01-19 Intel Corporation Pad cells for a 2/N mode clocking scheme
US5878264A (en) * 1997-07-17 1999-03-02 Sun Microsystems, Inc. Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure
US6122747A (en) * 1997-09-05 2000-09-19 First Pass Inc. Intelligent subsystem interface for modular hardware system
US6014729A (en) * 1997-09-29 2000-01-11 Firstpass, Inc. Shared memory arbitration apparatus and method
US5999876A (en) * 1998-04-01 1999-12-07 Cummins Engine Company, Inc. Method and system for communication with an engine control module in sleep mode
US6289465B1 (en) 1999-01-11 2001-09-11 International Business Machines Corporation System and method for power optimization in parallel units
JP4378847B2 (ja) * 2000-05-26 2009-12-09 ソニー株式会社 電子装置を使用する機器
US6823224B2 (en) 2001-02-21 2004-11-23 Freescale Semiconductor, Inc. Data processing system having an on-chip background debug system and method therefor
US7757094B2 (en) * 2001-02-27 2010-07-13 Qualcomm Incorporated Power management for subscriber identity module
JP3638271B2 (ja) * 2002-07-23 2005-04-13 沖電気工業株式会社 情報処理装置
US20050120185A1 (en) * 2003-12-01 2005-06-02 Sony Computer Entertainment Inc. Methods and apparatus for efficient multi-tasking
US8510485B2 (en) * 2007-08-31 2013-08-13 Apple Inc. Low power digital interface
US7793025B2 (en) * 2008-03-28 2010-09-07 Freescale Semiconductor, Inc. Hardware managed context sensitive interrupt priority level control
US9189048B2 (en) * 2008-09-10 2015-11-17 Apple Inc. Circuit having a low power mode
US8578384B2 (en) * 2009-10-28 2013-11-05 Freescale Semiconductor, Inc. Method and apparatus for activating system components
JP6122682B2 (ja) * 2013-04-16 2017-04-26 ルネサスエレクトロニクス株式会社 半導体装置及びそれを備えたプロセッサシステム
US10270434B2 (en) * 2016-02-18 2019-04-23 Apple Inc. Power saving with dynamic pulse insertion

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US4200912A (en) * 1978-07-31 1980-04-29 Motorola, Inc. Processor interrupt system
US4748559A (en) * 1979-08-09 1988-05-31 Motorola, Inc. Apparatus for reducing power consumed by a static microprocessor
US4758945A (en) * 1979-08-09 1988-07-19 Motorola, Inc. Method for reducing power consumed by a static microprocessor
US4443845A (en) * 1980-06-26 1984-04-17 Texas Instruments Incorporated Memory system having a common interface
GB2080585B (en) * 1980-07-22 1984-07-04 Tokyo Shibaura Electric Co Semiconductor integrated circuit with reduced power consumption
EP0048767B1 (de) * 1980-09-27 1985-03-20 Ibm Deutschland Gmbh Prioritätsstufengesteuerte Unterbrechungseinrichtung
JPS5775335A (en) * 1980-10-27 1982-05-11 Hitachi Ltd Data processor
JPS58127262A (ja) * 1982-01-25 1983-07-29 Toshiba Corp マイクロコンピユ−タ
IT1193650B (it) * 1983-01-31 1988-07-21 Honeywell Inf Systems Apparato di interruzione ad affidabilita' accresciuta
US4644547A (en) * 1984-06-28 1987-02-17 Westinghouse Electric Corp. Digital message format for two-way communication and control network
JPS63238630A (ja) * 1987-03-26 1988-10-04 Toshiba Corp マイクロプロセツサの割込み制御装置

Also Published As

Publication number Publication date
EP0368144A2 (de) 1990-05-16
JP2782367B2 (ja) 1998-07-30
EP0368144B1 (de) 1996-02-07
EP0368144A3 (en) 1990-11-14
US5361392A (en) 1994-11-01
JPH02187810A (ja) 1990-07-24
KR900008361A (ko) 1990-06-03
KR0147063B1 (ko) 1998-09-15
DE68925615T2 (de) 1996-09-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee