DE68924299T2 - Interface circuit. - Google Patents

Interface circuit.

Info

Publication number
DE68924299T2
DE68924299T2 DE68924299T DE68924299T DE68924299T2 DE 68924299 T2 DE68924299 T2 DE 68924299T2 DE 68924299 T DE68924299 T DE 68924299T DE 68924299 T DE68924299 T DE 68924299T DE 68924299 T2 DE68924299 T2 DE 68924299T2
Authority
DE
Germany
Prior art keywords
interface circuit
interface
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68924299T
Other languages
German (de)
Other versions
DE68924299D1 (en
Inventor
Michinori Intellectua Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE68924299D1 publication Critical patent/DE68924299D1/en
Publication of DE68924299T2 publication Critical patent/DE68924299T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/018Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806Interface arrangements
DE68924299T 1988-05-02 1989-05-02 Interface circuit. Expired - Fee Related DE68924299T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63109316A JP2583570B2 (en) 1988-05-02 1988-05-02 Interface circuit

Publications (2)

Publication Number Publication Date
DE68924299D1 DE68924299D1 (en) 1995-10-26
DE68924299T2 true DE68924299T2 (en) 1996-04-04

Family

ID=14507124

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68924299T Expired - Fee Related DE68924299T2 (en) 1988-05-02 1989-05-02 Interface circuit.

Country Status (5)

Country Link
US (1) US5072139A (en)
EP (1) EP0340720B1 (en)
JP (1) JP2583570B2 (en)
KR (1) KR920004343B1 (en)
DE (1) DE68924299T2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510745A (en) * 1987-07-29 1996-04-23 Fujitsu Limited High-speed electronic circuit having a cascode configuration
EP0432280A1 (en) * 1989-12-04 1991-06-19 Siemens Aktiengesellschaft Interface between two electrical circuits operating under different supply voltages
JP3028857B2 (en) * 1991-03-29 2000-04-04 株式会社日立製作所 Semiconductor integrated circuit device
DE10317213A1 (en) * 2003-04-15 2004-11-04 Robert Bosch Gmbh level converter
US8264272B2 (en) * 2009-04-22 2012-09-11 Microchip Technology Incorporated Digital control interface in heterogeneous multi-chip module

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3411017A (en) * 1965-03-30 1968-11-12 Army Usa Signal slicer circuit
US3348068A (en) * 1965-04-29 1967-10-17 Bell Telephone Labor Inc Threshold discriminator and zerocrossing detector
JPS56106427A (en) * 1980-01-25 1981-08-24 Mitsubishi Electric Corp Transister logical circuit
JPS59215122A (en) * 1983-05-23 1984-12-05 Fujitsu Ltd Transistor circuit
JPH0720059B2 (en) * 1984-05-23 1995-03-06 株式会社日立製作所 Transistor circuit
EP0329793B1 (en) * 1987-07-29 1995-10-25 Fujitsu Limited High-speed electronic circuit having a cascode configuration

Also Published As

Publication number Publication date
US5072139A (en) 1991-12-10
EP0340720B1 (en) 1995-09-20
KR890017884A (en) 1989-12-18
DE68924299D1 (en) 1995-10-26
JP2583570B2 (en) 1997-02-19
KR920004343B1 (en) 1992-06-01
EP0340720A2 (en) 1989-11-08
JPH01279623A (en) 1989-11-09
EP0340720A3 (en) 1990-03-28

Similar Documents

Publication Publication Date Title
FI890607A0 (en) Circuit arrangement.
DE58906492D1 (en) Semiconductor circuit.
DE3769564D1 (en) LOGICAL CIRCUIT.
DE3779784T2 (en) LOGICAL CIRCUIT.
DE69017601T2 (en) Circuit arrangement.
DE69008464T2 (en) Circuit arrangement.
DE68910413T2 (en) Output circuit.
DE68901985T2 (en) DELAY CIRCUIT.
DE68912739T2 (en) COMMAND CIRCUIT.
DE68915351D1 (en) Output circuit.
DE68916093D1 (en) Integrated circuit.
DE3673816D1 (en) INTERFACE CIRCUIT.
DE68920785D1 (en) Logical circuit.
DE68912198T2 (en) Telephone interface circuit.
NO884586L (en) INTERFACE DEVICES.
DE68924299D1 (en) Interface circuit.
DE68900686D1 (en) CIRCUIT SYSTEM.
DE3884713D1 (en) Logical circuit.
DE3787037T2 (en) Hold circuit.
DE68911196T2 (en) Operating circuit.
DE68923540T2 (en) Solid state circuit.
FI914230A0 (en) Circuit arrangement.
FI882612A0 (en) Circuit arrangement.
FI882619A0 (en) Circuit arrangement.
DE340777T1 (en) OPERATING CIRCUIT.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee