DE10317213A1 - Level converter - Google Patents

Level converter

Info

Publication number
DE10317213A1
DE10317213A1 DE2003117213 DE10317213A DE10317213A1 DE 10317213 A1 DE10317213 A1 DE 10317213A1 DE 2003117213 DE2003117213 DE 2003117213 DE 10317213 A DE10317213 A DE 10317213A DE 10317213 A1 DE10317213 A1 DE 10317213A1
Authority
DE
Germany
Prior art keywords
level
voltage
characterized
level converter
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE2003117213
Other languages
German (de)
Inventor
Peter Maue
Rainer Zuschlag
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE2003117213 priority Critical patent/DE10317213A1/en
Publication of DE10317213A1 publication Critical patent/DE10317213A1/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/018Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806Interface arrangements

Abstract

A level converter (LS) is proposed which has a transistor, to the first outer electrode of which an input voltage having a first and second level is connected and to whose second outer electrode an output voltage having a third and a fourth level is present. A supply voltage with the fourth level is connected to a center electrode of the transistor via a voltage divider. The transistor is wired in such a way that the first level leads to the third level and the second level leads to the fourth level on the second outer electrode.

Description

  • State of technology
  • The The invention is based on a level converter according to the type of the independent claim.
  • Out DE 101 20 672 A1 For example, a level converter is known in which a level is changed from a first DC voltage level to a second DC voltage level.
  • Advantages of invention
  • The level converter according to the invention with the characteristics of the independent In contrast, claims the advantage that this level converter has only one transistor that is wired in such a way that the logical input level is transferred to the output without inversion. This will be a Threshold voltage is used as the switching threshold that causes dependent on from your logical input level to the corresponding logical one Output level is switched. This is a very inexpensive and simple execution a level converter. The level converter should preferably be between a transmitter and a receiver Act. An advantageous circuit measure is the use of the pull-down resistor in order to blocking the transistor's output level to that of the pull-down resistor to pull the applied voltage. Under supply voltage is here understand any voltage provided to adjust the voltage Output level serves. This includes also voltages derived from the supply voltage, for example via voltage dividers to be provided.
  • The Input voltage, for example 0 / 3.3 V, is at a first outer electrode connected, for example the emitter. 0 V means for example Low and 3.3 V high. The output voltage can then be tapped at the collector. The logic output level is determined, for example, by the voltage across the pull-up resistor set, for example 5 V, preferably the supply voltage Recipient. This voltage of 5 V or the supply voltage has a value which the output voltage should reach at its maximum level. At an input level of 0 V, the output level will also be have a value of 0 V. The 5 V output level could be high correspond and the output level of 0 V Low. Other level conversions are possible.
  • by virtue of The level converter according to the invention is also special in terms of its simple construction space-saving. The outer electrode designate collector and emitter or source and drain, while the center electrode denotes the base or the gate.
  • By those in the dependent Measures listed claims and further developments are advantageous improvements of the independent claim specified level converter possible.
  • Especially It is advantageous that the transistor either as a bipolar transistor or as an n-channel field effect transistor can be trained. The base / drain voltage divider becomes Setting the threshold voltage, i.e. a switching threshold, is used. It is possible, to do without the voltage divider if a suitable voltage available in the affected system is. Furthermore, the resistance of the voltage divider, which is connected to ground, a capacitor in parallel on the for clean and ensures fast switching edges of the output signal. So that is enables a faithful reproduction of the input signal.
  • advantageously, is the level converter between a processor or microcontroller and a communication bus such as the CAN bus in a control unit for restraint systems connected. It is possible, that the level converter between circuits with different logical levels is used.
  • In another embodiment it is provided that the supply voltage of the receiver is not is used to adjust the threshold voltage, but only to adjust the output level. The threshold voltage will then dependent on set by the supply voltage of the transmitter. The supply voltage Recipient can then only be used, for example, to adjust the output level be used. This circuit measure enables easy follow-up of fluctuations in the respective supply voltages due to the Output level. Fluctuations in the supply voltage of the transmitter affect the switching behavior of the transistor and fluctuations the supply voltage of the receiver act directly on the output level.
  • drawing
  • embodiments the invention are shown in the drawing and are in the following description in more detail explained.
  • Show it 1 a block diagram, 2 a first circuit diagram of the level converter according to the invention and 3 a second circuit diagram of the level converter.
  • description
  • 1 shows in a block diagram the use of the level converter according to the invention. A microcontroller μC in a control unit for restraint systems is connected to the level converter LS via a data output. The level converter LS is connected to a CAN bus CAN via a data output. The microcontroller uses a maximum voltage level for its signals of 3.3 V. However, the CAN bus uses a voltage level of 5 V. Consequently, a level converter is required to convert the signals of the microcontroller from 3.3 V to 5 V.
  • 2 now shows the inventive design of the level converter. An input voltage is at an emitter of a transistor T1 20 connected, which has a low level and a high level. The low level is at 0 V, while the high level is at 3.3 V. On the one hand, a resistor R3 is connected to the collector of transistor T1 and, on the other hand, an output for an output voltage 21 , The output voltage 21 , which is intended here for the CAN bus, should also have a low level of 0 V, but a high level of 5 V. The resistor R3 is on its other side with a resistor R1 and a supply voltage VDD on an electrode 22 connected. The supply voltage VDD has a level of 5 V, ie exactly the level that the output voltage 21 should be at high level. The resistor R1 is connected on its other side to a base as the center electrode of the transistor T1 and to a parallel circuit comprising a resistor R2 and a capacitor C 1. The parallel connection of the capacitor C 1 and the resistor R2 is connected to ground on its other side.
  • Is now on a connection 20 the input voltage at the low level, i.e. 0 V, then the collector-emitter path of the transistor T1 is conductive, since the voltage VDD of 5 V across the voltage dividers R1 and R2 causes a voltage drop on the base-emitter path such that the transistor T1 is conductive. The voltage divider R1 and R2 must therefore take this into account. The result is that even at the exit 21 there is a low level of 0 V, since the transistor T1 is conductive and no significant voltage drops and on the other side at the connection 20 0 V are also present. Now go to the connection 20 the voltage from 0 V to the high level of 3.3 V, then this voltage change affects the resistors R3, R1 and R2 on the base-emitter voltage, which was previously at a level of 0 V at the input 20 was determined solely by the voltage VDD of 5 V. The one at the connector 20 Rising voltage thus reduces the base-emitter voltage, so that the transistor T1 is moved into the blocked region. This results in the switching behavior of the level converter. The dimensions of the resistors R3, R1 and R2 are such that the blocking of the collector-emitter path of the transistor T1 at 3.3 V is at least fulfilled. This voltage therefore serves as a threshold voltage. However, if transistor T1 is blocked, the full 5 V are present at resistor R3, since the current can no longer flow through transistor T1, but only through the output 21 , This 5 V accordingly causes the high level of 5 V.
  • The Capacitor C1 provides clean and fast switching edges of the S-V output signal to ensure a true to the original To allow playback of the input signal. The resistor R3 Fulfills so here the function of a so-called "pull-up resistor". It is possible here to use other voltage values.
  • Corresponding have to then the resistors R1, R2 and R3 and the capacitor C1 can be dimensioned. As Transistors for the transistor T1 can Bipolar transistors or n-channel field effect transistors are used become.
  • following Dimensioning example is possible: R1 = 34.8 kΩ, R2 = 21.5 kΩ, R3 = 3.48 kΩ, C1 = 22nF and T1 = BC846B.
  • 3 shows a further embodiment of the invention. The same designations are used here for the same components. The only difference to 2 is that the resistor R3 is now connected on the first side to the supply voltage VDD2 of the receiver and on the other side to the collector of T1 and the output 21 , In addition, R1 is connected to VDD1 on its first side. VDD1 denotes the transmitter supply voltage. On its second side, R1 is like in 2 connected to the base of T1 and the parallel connection of R2 and C1. Consequently, two supply voltages VDD1 and VDD2 are used for the circuit here. The threshold voltage for the transistor T1 is set via the supply voltage VDD1 of the transmitter and the output voltage via the supply voltage VDD2 of the receiver. The level converter according to the invention can thus also be used for slightly dynamic supply voltages, because either the dynamics of VDD 1 act on the threshold voltage and thus the switching behavior of the transistor and / or VDD2 acts directly on the output voltage of the level converter due to their dynamics. The high levels of the level converter correspond to the supply voltages of the transmitter and receiver.

Claims (10)

  1. Level converter, characterized in that the level converter (LS) has a transistor (T1), on the first outer electrode of which an input voltage ( 20 ) is connected to a first and second level and an output voltage ( 21 ) is present at a third and fourth level, that a threshold voltage is present at a center electrode of the transistor (T1), that a supply voltage (VDD) is present at a fourth level and that the transistor (T1) is connected such that the first level is third Level and the second level lead to the fourth level on the second outer electrode.
  2. Level converter according to claim 1, characterized in that a pull-up resistor (R3) between the supply voltage (VDD) and the second outer electrode is provided.
  3. Level converter according to claim 1 or 2, characterized in that that a voltage divider (R1, R2) for setting the threshold voltage is provided.
  4. Level converter according to claim 3, characterized in that a capacitor (C) is provided in the voltage divider (R1, R2) is used to stabilize the threshold voltage.
  5. Level converter according to one of the preceding claims, characterized characterized in that the transistor (T1) is an NPN bipolar transistor is.
  6. Level converter according to one of claims 1 to 3, characterized in that the transistor is an n-channel field effect transistor.
  7. Level converter according to one of the preceding claims, characterized characterized in that the first and the third level 0 V, the second Level is 3.3 V and the fourth level is 5 V.
  8. Level converter according to one of the preceding claims, characterized characterized in that the level converter (LS) between a processor (μC) and a communication bus (CAN) is connected in a control unit for restraint systems.
  9. Level converter according to claim 1, characterized in that the threshold voltage is dependent on the second level is set.
  10. Level converter according to claim 1, characterized in that the threshold voltage is dependent on the fourth level is set.
DE2003117213 2003-04-15 2003-04-15 Level converter Withdrawn DE10317213A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE2003117213 DE10317213A1 (en) 2003-04-15 2003-04-15 Level converter

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE2003117213 DE10317213A1 (en) 2003-04-15 2003-04-15 Level converter
PCT/DE2004/000289 WO2004093321A1 (en) 2003-04-15 2004-02-17 Level converter
DE112004001095T DE112004001095D2 (en) 2003-04-15 2004-02-17 Level converter

Publications (1)

Publication Number Publication Date
DE10317213A1 true DE10317213A1 (en) 2004-11-04

Family

ID=33103387

Family Applications (2)

Application Number Title Priority Date Filing Date
DE2003117213 Withdrawn DE10317213A1 (en) 2003-04-15 2003-04-15 Level converter
DE112004001095T Expired - Fee Related DE112004001095D2 (en) 2003-04-15 2004-02-17 Level converter

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE112004001095T Expired - Fee Related DE112004001095D2 (en) 2003-04-15 2004-02-17 Level converter

Country Status (2)

Country Link
DE (2) DE10317213A1 (en)
WO (1) WO2004093321A1 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL282779A (en) * 1961-09-08
US3852617A (en) * 1973-01-02 1974-12-03 Int Video Corp Apparatus for level shifting independent of signal amplitude having a passive peak detector
JPS5639632A (en) * 1979-09-07 1981-04-15 Fujitsu Ltd Multiple input logic circuit
US4605864A (en) * 1985-01-04 1986-08-12 Advanced Micro Devices, Inc. AFL (advanced fast logic) line driver circuit
DE3854617D1 (en) * 1987-07-29 1995-11-30 Fujitsu Ltd Electronic high-speed circuit in cascode configuration.
JP2583570B2 (en) * 1988-05-02 1997-02-19 株式会社東芝 Interface circuit
DE4219559A1 (en) * 1992-06-15 1993-12-16 Siemens Ag Logic level converter for TTL input - provides output with smaller level shift at junction of resistance and chain of bipolar and two complementary MOS transistors
JP3152867B2 (en) * 1995-08-25 2001-04-03 株式会社東芝 Level shift semiconductor device

Also Published As

Publication number Publication date
WO2004093321A1 (en) 2004-10-28
DE112004001095D2 (en) 2006-02-23

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