DE68923530D1 - Speicheranordnung mit Felder und der Möglichkeit von sich abwechselnden Datentoren. - Google Patents

Speicheranordnung mit Felder und der Möglichkeit von sich abwechselnden Datentoren.

Info

Publication number
DE68923530D1
DE68923530D1 DE68923530T DE68923530T DE68923530D1 DE 68923530 D1 DE68923530 D1 DE 68923530D1 DE 68923530 T DE68923530 T DE 68923530T DE 68923530 T DE68923530 T DE 68923530T DE 68923530 D1 DE68923530 D1 DE 68923530D1
Authority
DE
Germany
Prior art keywords
fields
possibility
storage arrangement
alternating data
data gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923530T
Other languages
English (en)
Other versions
DE68923530T2 (de
Inventor
Frederick John Aichelmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68923530D1 publication Critical patent/DE68923530D1/de
Application granted granted Critical
Publication of DE68923530T2 publication Critical patent/DE68923530T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
DE68923530T 1988-10-25 1989-10-10 Speicheranordnung mit Felder und der Möglichkeit von sich abwechselnden Datentoren. Expired - Fee Related DE68923530T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/262,560 US5150328A (en) 1988-10-25 1988-10-25 Memory organization with arrays having an alternate data port facility

Publications (2)

Publication Number Publication Date
DE68923530D1 true DE68923530D1 (de) 1995-08-24
DE68923530T2 DE68923530T2 (de) 1996-02-29

Family

ID=22998027

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923530T Expired - Fee Related DE68923530T2 (de) 1988-10-25 1989-10-10 Speicheranordnung mit Felder und der Möglichkeit von sich abwechselnden Datentoren.

Country Status (4)

Country Link
US (1) US5150328A (de)
EP (1) EP0366588B1 (de)
JP (1) JPH06101224B2 (de)
DE (1) DE68923530T2 (de)

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US5293236A (en) * 1991-01-11 1994-03-08 Fuji Photo Film Co., Ltd. Electronic still camera including an EEPROM memory card and having a continuous shoot mode
US5295255A (en) * 1991-02-22 1994-03-15 Electronic Professional Services, Inc. Method and apparatus for programming a solid state processor with overleaved array memory modules
DE4135553A1 (de) * 1991-10-29 1993-05-06 Alcatel Sel Aktiengesellschaft, 7000 Stuttgart, De Verfahren und schaltungsanordnung zur datenblockuebertragung ueber ein bussystem
US5278800A (en) * 1991-10-31 1994-01-11 International Business Machines Corporation Memory system and unique memory chip allowing island interlace
US5321697A (en) * 1992-05-28 1994-06-14 Cray Research, Inc. Solid state storage device
JPH06250931A (ja) * 1993-02-26 1994-09-09 Mitsubishi Electric Corp 情報処理装置
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
US5524267A (en) * 1994-03-31 1996-06-04 International Business Machines Corporation Digital I/O bus controller circuit with auto-incrementing, auto-decrementing and non-incrementing/decrementing access data ports
US5590078A (en) * 1994-10-07 1996-12-31 Mukesh Chatter Method of and apparatus for improved dynamic random access memory (DRAM) providing increased data bandwidth and addressing range for current DRAM devices and/or equivalent bandwidth and addressing range for smaller DRAM devices
US5537353A (en) * 1995-08-31 1996-07-16 Cirrus Logic, Inc. Low pin count-wide memory devices and systems and methods using the same
US5867736A (en) * 1996-03-29 1999-02-02 Lsi Logic Corporation Methods for simplified integration of host based storage array control functions using read and write operations on a storage array control port
US6249470B1 (en) 1999-12-03 2001-06-19 International Business Machines Corporation Bi-directional differential low power sense amp and memory system
US8279886B2 (en) * 2004-12-30 2012-10-02 Intel Corporation Dataport and methods thereof
US7269088B2 (en) * 2005-05-17 2007-09-11 Intel Corporation Identical chips with different operations in a system
US7725609B2 (en) * 2005-08-05 2010-05-25 Qimonda Ag System memory device having a dual port
CN109348730B (zh) * 2015-09-18 2022-05-24 株式会社日立制作所 存储器控制器、存储器控制方法以及半导体存储装置
US11392494B2 (en) * 2020-06-05 2022-07-19 Intel Corporation Technologies for performant column read operations on clustered data in a dimm architecture

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US4028675A (en) * 1973-05-14 1977-06-07 Hewlett-Packard Company Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
US4020466A (en) * 1974-07-05 1977-04-26 Ibm Corporation Memory hierarchy system with journaling and copy back
JPS5345939A (en) * 1976-10-07 1978-04-25 Sharp Corp Ram circuit
US4125877A (en) * 1976-11-26 1978-11-14 Motorola, Inc. Dual port random access memory storage cell
JPS5532288A (en) * 1978-08-29 1980-03-06 Nec Corp Lsi memory
US4349870A (en) * 1979-09-05 1982-09-14 Motorola, Inc. Microcomputer with programmable multi-function port
US4443864A (en) * 1979-10-09 1984-04-17 Texas Instruments Incorporated Memory system for microprocessor with multiplexed address/data bus
US4443845A (en) * 1980-06-26 1984-04-17 Texas Instruments Incorporated Memory system having a common interface
US4410964A (en) * 1980-12-08 1983-10-18 Nordling Karl I Memory device having a plurality of output ports
US4395765A (en) * 1981-04-23 1983-07-26 Bell Telephone Laboratories, Incorporated Multiport memory array
US4394726A (en) * 1981-04-29 1983-07-19 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Distributed multiport memory architecture
US4491937A (en) * 1982-02-25 1985-01-01 Trw Inc. Multiport register file
US4541076A (en) * 1982-05-13 1985-09-10 Storage Technology Corporation Dual port CMOS random access memory
US4489381A (en) * 1982-08-06 1984-12-18 International Business Machines Corporation Hierarchical memories having two ports at each subordinate memory level
US4535427A (en) * 1982-12-06 1985-08-13 Mostek Corporation Control of serial memory
US4554645A (en) * 1983-03-10 1985-11-19 International Business Machines Corporation Multi-port register implementation
US4566082A (en) * 1983-03-23 1986-01-21 Tektronix, Inc. Memory pack addressing system
US4577292A (en) * 1983-05-31 1986-03-18 International Business Machines Corporation Support circuitry for multi-port systems
JPS604383A (ja) * 1983-06-22 1985-01-10 Matsushita Electric Ind Co Ltd テレビジヨン信号デジタル磁気記録再生装置
US4580245A (en) * 1983-07-28 1986-04-01 Sperry Corporation Complementary metal oxide semiconductor dual port random access memory cell
JPS6072020A (ja) * 1983-09-29 1985-04-24 Nec Corp デュアルポ−トメモリ回路
US4586168A (en) * 1983-12-12 1986-04-29 Motorola, Inc. Dual port memory sense amplifier isolation
US4573116A (en) * 1983-12-20 1986-02-25 Honeywell Information Systems Inc. Multiword data register array having simultaneous read-write capability
US4649475A (en) * 1984-04-02 1987-03-10 Sperry Corporation Multiple port memory with port decode error detector
US4718039A (en) * 1984-06-29 1988-01-05 International Business Machines Intermediate memory array with a parallel port and a buffered serial port
FR2569290B1 (fr) * 1984-08-14 1986-12-05 Trt Telecom Radio Electr Processeur pour le traitement de signal et structure de multitraitement hierarchisee comportant au moins un tel processeur
US4663741A (en) * 1984-10-16 1987-05-05 Trilogy Systems Corporation Strobed access semiconductor memory system
US4623990A (en) * 1984-10-31 1986-11-18 Advanced Micro Devices, Inc. Dual-port read/write RAM with single array
IT1177400B (it) * 1984-12-12 1987-08-26 Honeywell Inf Systems Sistema a microprocessore
US4627030A (en) * 1985-02-04 1986-12-02 At&T Bell Laboratories Dual port memory word size expansion technique
JPS61221938A (ja) * 1985-03-28 1986-10-02 Toshiba Corp シ−ケンス回路
US4731758A (en) * 1985-06-21 1988-03-15 Advanced Micro Devices, Inc. Dual array memory with inter-array bi-directional data transfer
US4719601A (en) * 1986-05-02 1988-01-12 International Business Machine Corporation Column redundancy for two port random access memory
US4742493A (en) * 1986-05-19 1988-05-03 Advanced Micro Devices, Inc. Multiple port memory array device including improved timing and associated method

Also Published As

Publication number Publication date
JPH02123589A (ja) 1990-05-11
EP0366588B1 (de) 1995-07-19
EP0366588A3 (de) 1991-11-06
JPH06101224B2 (ja) 1994-12-12
US5150328A (en) 1992-09-22
EP0366588A2 (de) 1990-05-02
DE68923530T2 (de) 1996-02-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee