DE68923021T2 - Mikrocomputersystem, fähig zum Speicherzugriff mit hoher Geschwindigkeit. - Google Patents

Mikrocomputersystem, fähig zum Speicherzugriff mit hoher Geschwindigkeit.

Info

Publication number
DE68923021T2
DE68923021T2 DE68923021T DE68923021T DE68923021T2 DE 68923021 T2 DE68923021 T2 DE 68923021T2 DE 68923021 T DE68923021 T DE 68923021T DE 68923021 T DE68923021 T DE 68923021T DE 68923021 T2 DE68923021 T2 DE 68923021T2
Authority
DE
Germany
Prior art keywords
high speed
memory access
system capable
microcomputer system
microcomputer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923021T
Other languages
English (en)
Other versions
DE68923021D1 (de
Inventor
Yukihiro Nishiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63066455A external-priority patent/JPH0769797B2/ja
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE68923021D1 publication Critical patent/DE68923021D1/de
Publication of DE68923021T2 publication Critical patent/DE68923021T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
DE68923021T 1988-03-18 1989-03-20 Mikrocomputersystem, fähig zum Speicherzugriff mit hoher Geschwindigkeit. Expired - Fee Related DE68923021T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63066455A JPH0769797B2 (ja) 1988-03-18 1988-03-18 マイクロコンピュータシステム
JP12884288 1988-05-25

Publications (2)

Publication Number Publication Date
DE68923021D1 DE68923021D1 (de) 1995-07-20
DE68923021T2 true DE68923021T2 (de) 1996-02-22

Family

ID=26407647

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923021T Expired - Fee Related DE68923021T2 (de) 1988-03-18 1989-03-20 Mikrocomputersystem, fähig zum Speicherzugriff mit hoher Geschwindigkeit.

Country Status (3)

Country Link
US (1) US5151983A (de)
EP (1) EP0333231B1 (de)
DE (1) DE68923021T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1146249A (zh) * 1994-04-13 1997-03-26 艾利森公司 大存储器的高效寻址
US5592425A (en) * 1995-12-20 1997-01-07 Intel Corporation Method and apparatus for testing a memory where data is passed through the memory for comparison with data read from the memory
FR2757305B1 (fr) * 1996-12-17 1999-01-15 Sgs Thomson Microelectronics Dispositif et procede de lecture incrementale d'une memoire
FR2757306B1 (fr) * 1996-12-17 1999-01-15 Sgs Thomson Microelectronics Procede et dispositif de lecture avec prediction d'une memoire
US10983936B2 (en) * 2019-02-27 2021-04-20 Microchip Technology Incorporated Programmable arbitrary sequence direct memory access controller for configuring multiple core independent peripherals

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969724A (en) * 1975-04-04 1976-07-13 The Warner & Swasey Company Central processing unit for use in a microprocessor
US4293908A (en) * 1979-01-31 1981-10-06 Honeywell Information Systems Inc. Data processing system having direct memory access bus cycle
US4280199A (en) * 1979-08-03 1981-07-21 Sony Corporation Apparatus for scanning an addressable memory
US4613953A (en) * 1983-04-22 1986-09-23 Ncr Corporation Paging register for memory devices
JPH0799616B2 (ja) * 1984-08-30 1995-10-25 三菱電機株式会社 半導体記憶装置
US4750839A (en) * 1985-08-07 1988-06-14 Texas Instruments Incorporated Semiconductor memory with static column decode and page mode addressing capability
JPH083956B2 (ja) * 1986-09-18 1996-01-17 日本テキサス・インスツルメンツ株式会社 半導体記憶装置
US4802125A (en) * 1986-11-21 1989-01-31 Nec Corporation Memory access control apparatus

Also Published As

Publication number Publication date
EP0333231A2 (de) 1989-09-20
DE68923021D1 (de) 1995-07-20
EP0333231B1 (de) 1995-06-14
US5151983A (en) 1992-09-29
EP0333231A3 (de) 1992-03-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee