DE68918966D1 - System zur Steuerung der Datenübertragung. - Google Patents

System zur Steuerung der Datenübertragung.

Info

Publication number
DE68918966D1
DE68918966D1 DE68918966T DE68918966T DE68918966D1 DE 68918966 D1 DE68918966 D1 DE 68918966D1 DE 68918966 T DE68918966 T DE 68918966T DE 68918966 T DE68918966 T DE 68918966T DE 68918966 D1 DE68918966 D1 DE 68918966D1
Authority
DE
Germany
Prior art keywords
data transmission
controlling data
controlling
transmission
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68918966T
Other languages
English (en)
Other versions
DE68918966T2 (de
Inventor
Takayoshi Taniai
Tadashi Saitoh
Yasuhiro Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Electronics Inc
Original Assignee
Fujitsu Ltd
Fujitsu Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Electronics Inc filed Critical Fujitsu Ltd
Publication of DE68918966D1 publication Critical patent/DE68918966D1/de
Application granted granted Critical
Publication of DE68918966T2 publication Critical patent/DE68918966T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/762—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks
DE68918966T 1988-03-04 1989-03-02 System zur Steuerung der Datenübertragung. Expired - Fee Related DE68918966T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63051223A JP2527458B2 (ja) 1988-03-04 1988-03-04 デ―タ転送制御装置

Publications (2)

Publication Number Publication Date
DE68918966D1 true DE68918966D1 (de) 1994-12-01
DE68918966T2 DE68918966T2 (de) 1995-03-02

Family

ID=12880940

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68918966T Expired - Fee Related DE68918966T2 (de) 1988-03-04 1989-03-02 System zur Steuerung der Datenübertragung.

Country Status (5)

Country Link
US (1) US5043935A (de)
EP (1) EP0331487B1 (de)
JP (1) JP2527458B2 (de)
KR (1) KR920002831B1 (de)
DE (1) DE68918966T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594927A (en) * 1992-01-09 1997-01-14 Digital Equipment Corporation Apparatus and method for aligning data transferred via DMA using a barrel shifter and a buffer comprising of byte-wide, individually addressabe FIFO circuits
WO1994019747A1 (en) * 1993-02-17 1994-09-01 3Com Corporation System for reading dynamically changing data
JP3566364B2 (ja) * 1994-12-22 2004-09-15 キヤノン株式会社 データ処理装置及び方法
US5701517A (en) * 1994-12-22 1997-12-23 Cirrus Logic, Inc. Pipelined alignment shifter and method for universal bit field boundary alignment
US6381690B1 (en) * 1995-08-01 2002-04-30 Hewlett-Packard Company Processor for performing subword permutations and combinations
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
JPH1078934A (ja) * 1996-07-01 1998-03-24 Sun Microsyst Inc パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム
GB2399900B (en) * 2003-03-27 2005-10-05 Micron Technology Inc Data reording processor and method for use in an active memory device
WO2005122177A1 (ja) * 2004-06-09 2005-12-22 Matsushita Electric Industrial Co., Ltd. 半導体集積回路

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4188664A (en) * 1977-11-15 1980-02-12 Phillips Petroleum Company I/O Terminal identification
US4309755A (en) * 1979-08-22 1982-01-05 Bell Telephone Laboratories, Incorporated Computer input/output arrangement for enabling a simultaneous read/write data transfer
JPS5833972B2 (ja) * 1979-11-12 1983-07-23 富士通株式会社 計算機システム間通信方式
JPS57120146A (en) * 1981-01-16 1982-07-27 Hitachi Ltd Data transfer device
JPS5833770A (ja) * 1981-08-24 1983-02-28 Sony Corp デジタルデ−タのプログラム転送方法
US4514823A (en) * 1982-01-15 1985-04-30 International Business Machines Corporation Apparatus and method for extending a parallel channel to a serial I/O device
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system
KR900007564B1 (ko) * 1984-06-26 1990-10-15 모토로라 인코포레이티드 동적 버스를 갖는 데이터 처리기
WO1986000431A1 (en) * 1984-06-27 1986-01-16 Motorola, Inc. Data processor having multiple bus cycle operand cycles
DE3525898A1 (de) * 1985-07-19 1987-01-29 Reinhard Lidzba Verfahren zum komprimieren und dekomprimieren mehrerer strukturverwandter datenfolgen sowie einrichtungen zur durchfuehrung des verfahrens
JPS62184531A (ja) * 1986-02-10 1987-08-12 Hitachi Ltd バレルシフタ
JPS6428752A (en) * 1987-07-24 1989-01-31 Toshiba Corp Data processor
US4855900A (en) * 1987-10-28 1989-08-08 Recognition Equipment Incorporated System for transferring data to a mainframe computer

Also Published As

Publication number Publication date
EP0331487A2 (de) 1989-09-06
EP0331487A3 (en) 1990-10-31
KR920002831B1 (ko) 1992-04-04
US5043935A (en) 1991-08-27
JP2527458B2 (ja) 1996-08-21
EP0331487B1 (de) 1994-10-26
KR890015108A (ko) 1989-10-28
DE68918966T2 (de) 1995-03-02
JPH01224857A (ja) 1989-09-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee