DE60320219D1 - Aufteilung der stromspeisungs- und massefläche und kontaktlöcher mittels kanälen / gräben zur stromversorgung - Google Patents

Aufteilung der stromspeisungs- und massefläche und kontaktlöcher mittels kanälen / gräben zur stromversorgung

Info

Publication number
DE60320219D1
DE60320219D1 DE60320219T DE60320219T DE60320219D1 DE 60320219 D1 DE60320219 D1 DE 60320219D1 DE 60320219 T DE60320219 T DE 60320219T DE 60320219 T DE60320219 T DE 60320219T DE 60320219 D1 DE60320219 D1 DE 60320219D1
Authority
DE
Germany
Prior art keywords
curries
channels
electricity
distribution
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60320219T
Other languages
English (en)
Other versions
DE60320219T2 (de
Inventor
Daryl Sato
Gary Brist
Gary Long
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60320219D1 publication Critical patent/DE60320219D1/de
Application granted granted Critical
Publication of DE60320219T2 publication Critical patent/DE60320219T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0221—Coaxially shielded signal lines comprising a continuous shielding layer partially or wholly surrounding the signal lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H05K2201/09518—Deep blind vias, i.e. blind vias connecting the surface circuit to circuit layers deeper than the first buried circuit layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09981—Metallised walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0108—Male die used for patterning, punching or transferring
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/005—Punching of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Connector Housings Or Holding Contact Members (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Non-Insulated Conductors (AREA)
DE60320219T 2002-02-04 2003-01-23 Aufteilung von strom-und erdungsebenen und durchkontaktverbindung zur nutzung von kanälen/gräben zur stromzufuhr Expired - Lifetime DE60320219T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US68229 2002-02-04
US10/068,229 US6747216B2 (en) 2002-02-04 2002-02-04 Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery
PCT/US2003/002360 WO2003067943A2 (en) 2002-02-04 2003-01-23 Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery

Publications (2)

Publication Number Publication Date
DE60320219D1 true DE60320219D1 (de) 2008-05-21
DE60320219T2 DE60320219T2 (de) 2009-05-14

Family

ID=27658997

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60320219T Expired - Lifetime DE60320219T2 (de) 2002-02-04 2003-01-23 Aufteilung von strom-und erdungsebenen und durchkontaktverbindung zur nutzung von kanälen/gräben zur stromzufuhr

Country Status (7)

Country Link
US (5) US6747216B2 (de)
EP (1) EP1472914B1 (de)
CN (1) CN1625925B (de)
AT (1) ATE392126T1 (de)
AU (1) AU2003207694A1 (de)
DE (1) DE60320219T2 (de)
WO (1) WO2003067943A2 (de)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002352783A1 (en) * 2001-11-20 2003-06-10 The Regents Of The University Of California Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications
US7371659B1 (en) * 2001-12-12 2008-05-13 Lsi Logic Corporation Substrate laser marking
US6747216B2 (en) * 2002-02-04 2004-06-08 Intel Corporation Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery
US6743049B2 (en) * 2002-06-24 2004-06-01 Advanced Interconnections Corporation High speed, high density interconnection device
US7038917B2 (en) * 2002-12-27 2006-05-02 Vlt, Inc. Low loss, high density array interconnection
US20040219342A1 (en) * 2003-01-07 2004-11-04 Boggs David W. Electronic substrate with direct inner layer component interconnection
TWI297095B (en) * 2003-10-02 2008-05-21 Au Optronics Corp Bonding pad structure for a display and fabrication method thereof
US20050123860A1 (en) * 2003-12-03 2005-06-09 Paul Koning Dielectric with fluorescent material
US7265299B2 (en) * 2004-03-04 2007-09-04 Au Optronics Corporation Method for reducing voltage drop across metal lines of electroluminescence display devices
US7145083B2 (en) * 2004-07-13 2006-12-05 Nortel Networks Limited Reducing or eliminating cross-talk at device-substrate interface
KR20060008021A (ko) * 2004-07-23 2006-01-26 삼성전자주식회사 인쇄회로기판 및 이를 이용한 평판표시장치
US7262368B2 (en) * 2004-08-13 2007-08-28 Tessera, Inc. Connection structures for microelectronic devices and methods for forming such structures
WO2007046271A1 (ja) * 2005-10-18 2007-04-26 Nec Corporation 垂直信号経路、それを有するプリント基板及びそのプリント基板と半導体素子とを有する半導体パッケージ
US20070145595A1 (en) * 2005-12-27 2007-06-28 Hall Stephen H High speed interconnect
US20070274656A1 (en) * 2005-12-30 2007-11-29 Brist Gary A Printed circuit board waveguide
US7480435B2 (en) * 2005-12-30 2009-01-20 Intel Corporation Embedded waveguide printed circuit board structure
US20070154157A1 (en) * 2005-12-30 2007-07-05 Horine Bryce D Quasi-waveguide printed circuit board structure
US7800459B2 (en) 2006-12-29 2010-09-21 Intel Corporation Ultra-high bandwidth interconnect for data transmission
US8946873B2 (en) * 2007-08-28 2015-02-03 Micron Technology, Inc. Redistribution structures for microfeature workpieces
US7550853B2 (en) * 2007-10-10 2009-06-23 Itt Manufacturing Enterprises, Inc. Electrical isolation of monolithic circuits using a conductive through-hole in the substrate
US8249532B2 (en) * 2008-02-29 2012-08-21 Sierra Wireless, Inc. Radio communication apparatus
US8334590B1 (en) 2008-09-04 2012-12-18 Amkor Technology, Inc. Semiconductor device having insulating and interconnection layers
JP5304185B2 (ja) * 2008-11-10 2013-10-02 富士通株式会社 プリント配線板および電子装置
KR101018785B1 (ko) * 2008-11-28 2011-03-03 삼성전기주식회사 전자기 밴드갭 구조물 및 회로 기판
US8134086B2 (en) * 2009-02-17 2012-03-13 Lockheed Martin Corporation Electrical isolating structure for conductors in a substrate
TWI384925B (zh) * 2009-03-17 2013-02-01 Advanced Semiconductor Eng 內埋式線路基板之結構及其製造方法
US8432022B1 (en) * 2009-09-29 2013-04-30 Amkor Technology, Inc. Shielded embedded electronic component substrate fabrication method and structure
US8264848B2 (en) * 2009-10-30 2012-09-11 Research In Motion Limited Electrical assembly having impedance controlled signal traces
US8148823B1 (en) * 2009-12-14 2012-04-03 Picor Corporation Low loss package for electronic device
US8429735B2 (en) * 2010-01-26 2013-04-23 Frampton E. Ellis Method of using one or more secure private networks to actively configure the hardware of a computer or microchip
US8679280B2 (en) 2010-05-27 2014-03-25 International Business Machines Corporation Laser ablation of adhesive for integrated circuit fabrication
US8388782B2 (en) 2010-05-27 2013-03-05 International Business Machines Corporation Handler attachment for integrated circuit fabrication
US8419895B2 (en) 2010-05-27 2013-04-16 International Business Machines Corporation Laser ablation for integrated circuit fabrication
KR101109190B1 (ko) * 2010-06-04 2012-01-30 삼성전기주식회사 인쇄회로기판 및 그 제조방법
DE102011077206B4 (de) 2011-06-08 2019-01-31 Zf Friedrichshafen Ag Leiterplatte und Steuergerät für ein Getriebe eines Fahrzeugs mit der Leiterplatte
US9668859B2 (en) 2011-08-05 2017-06-06 California Institute Of Technology Percutaneous heart valve delivery systems
US9860985B1 (en) 2012-12-17 2018-01-02 Lockheed Martin Corporation System and method for improving isolation in high-density laminated printed circuit boards
WO2014144247A1 (en) 2013-03-15 2014-09-18 Arash Kheradvar Handle mechanism and functionality for repositioning and retrieval of transcatheter heart valves
US9136624B1 (en) * 2013-03-28 2015-09-15 Juniper Networks, Inc. Orthogonal cross-connecting of printed circuit boards without a midplane board
KR20140144487A (ko) * 2013-06-11 2014-12-19 에스케이하이닉스 주식회사 패키지 기판 및 제조 방법
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates
CN106817836A (zh) * 2015-12-02 2017-06-09 富葵精密组件(深圳)有限公司 电路板及其制作方法
JP7145068B2 (ja) * 2018-12-28 2022-09-30 新光電気工業株式会社 配線基板及びその製造方法
US11439002B2 (en) * 2019-10-28 2022-09-06 Nvidia Corporation Inter-layer slot for increasing printed circuit board power performance

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE435091B (sv) * 1983-01-31 1984-09-03 Ergonomen Hb Spenne for ett band spenne for ett band
US4967314A (en) * 1988-03-28 1990-10-30 Prime Computer Inc. Circuit board construction
JP2767645B2 (ja) * 1990-03-07 1998-06-18 富士通株式会社 多層配線基板の製造方法
JP2739726B2 (ja) * 1990-09-27 1998-04-15 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン 多層プリント回路板
US5129142A (en) * 1990-10-30 1992-07-14 International Business Machines Corporation Encapsulated circuitized power core alignment and lamination
US5473120A (en) * 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
US5304743A (en) * 1992-05-12 1994-04-19 Lsi Logic Corporation Multilayer IC semiconductor package
US5489554A (en) * 1992-07-21 1996-02-06 Hughes Aircraft Company Method of making a 3-dimensional circuit assembly having electrical contacts that extend through the IC layer
JP3241139B2 (ja) 1993-02-04 2001-12-25 三菱電機株式会社 フィルムキャリア信号伝送線路
US5527741A (en) * 1994-10-11 1996-06-18 Martin Marietta Corporation Fabrication and structures of circuit modules with flexible interconnect layers
US5512514A (en) * 1994-11-08 1996-04-30 Spider Systems, Inc. Self-aligned via and contact interconnect manufacturing method
JP2638567B2 (ja) * 1995-06-08 1997-08-06 日本電気株式会社 多層配線基板
US5745984A (en) * 1995-07-10 1998-05-05 Martin Marietta Corporation Method for making an electronic module
US6631558B2 (en) * 1996-06-05 2003-10-14 Laservia Corporation Blind via laser drilling system
JP4195731B2 (ja) * 1996-07-25 2008-12-10 富士通株式会社 多層プリント板及びこれを利用した高周波回路装置
US5912809A (en) * 1997-01-21 1999-06-15 Dell Usa, L.P. Printed circuit board (PCB) including channeled capacitive plane structure
US6119338A (en) * 1998-03-19 2000-09-19 Industrial Technology Research Institute Method for manufacturing high-density multilayer printed circuit boards
US6000120A (en) * 1998-04-16 1999-12-14 Motorola, Inc. Method of making coaxial transmission lines on a printed circuit board
US6713685B1 (en) * 1998-09-10 2004-03-30 Viasystems Group, Inc. Non-circular micro-via
US20020130739A1 (en) * 1998-09-10 2002-09-19 Cotton Martin A. Embedded waveguide and embedded electromagnetic shielding
US6214445B1 (en) * 1998-12-25 2001-04-10 Ngk Spark Plug Co., Ltd. Printed wiring board, core substrate, and method for fabricating the core substrate
US6452117B2 (en) * 1999-08-26 2002-09-17 International Business Machines Corporation Method for filling high aspect ratio via holes in electronic substrates and the resulting holes
US6444922B1 (en) * 1999-11-18 2002-09-03 Nortel Networks Limited Zero cross-talk signal line design
US6441313B1 (en) * 1999-11-23 2002-08-27 Sun Microsystems, Inc. Printed circuit board employing lossy power distribution network to reduce power plane resonances
US7061095B2 (en) * 2001-09-26 2006-06-13 Intel Corporation Printed circuit board conductor channeling
US6747216B2 (en) * 2002-02-04 2004-06-08 Intel Corporation Power-ground plane partitioning and via connection to utilize channel/trenches for power delivery
US6995322B2 (en) * 2003-01-30 2006-02-07 Endicott Interconnect Technologies, Inc. High speed circuitized substrate with reduced thru-hole stub, method for fabrication and information handling system utilizing same

Also Published As

Publication number Publication date
US20030205407A1 (en) 2003-11-06
US20080029296A1 (en) 2008-02-07
AU2003207694A8 (en) 2003-09-02
US6747216B2 (en) 2004-06-08
ATE392126T1 (de) 2008-04-15
CN1625925B (zh) 2010-05-26
US8299369B2 (en) 2012-10-30
EP1472914A2 (de) 2004-11-03
US7797826B2 (en) 2010-09-21
US8056221B2 (en) 2011-11-15
AU2003207694A1 (en) 2003-09-02
US7269899B2 (en) 2007-09-18
US20100038127A1 (en) 2010-02-18
US20030146020A1 (en) 2003-08-07
EP1472914B1 (de) 2008-04-09
DE60320219T2 (de) 2009-05-14
CN1625925A (zh) 2005-06-08
WO2003067943A2 (en) 2003-08-14
WO2003067943A3 (en) 2003-11-06
US20080029295A1 (en) 2008-02-07

Similar Documents

Publication Publication Date Title
DE60320219D1 (de) Aufteilung der stromspeisungs- und massefläche und kontaktlöcher mittels kanälen / gräben zur stromversorgung
ATE318116T1 (de) Elektrophysiologische elektrode mit mehreren energieversorgungsleitungen
WO2012061183A3 (en) Flexible led device for thermal management and method of making
ATE389113T1 (de) Elektrodenadressierungsverfahren
WO2008048677A3 (en) Electrified ceiling framework
TW200711221A (en) Artificial impedance structure
CL2008001440A1 (es) Montaje de conector electrico para un conductor principal y un conductor de derivacion,compuesto por dos miembros conductores que comprenden una pluralidad de canales de diferente profundidad para acomodar los conductores de acuerdo a sus diametros.
MX2011006865A (es) Ensamblado ionizador de electrodos de aire.
TW200627653A (en) Interconnection structure through passive component
DE60216433D1 (de) Lothöckermetallurgieschienen für versorgungs- und massenleitungsführung
WO2007089292A3 (en) Power management for wireless devices
DE60322253D1 (de) Batterieverbinder
TW200715640A (en) Methods and apparatus for symmetrical and/or concentric radio frequency matching networks
TW200633322A (en) Connector
TW200711194A (en) Organic based device and method for manufacture thereof
WO2010062509A3 (en) Electrified ceiling grid
IN2013CN00307A (de)
MX2015003042A (es) Conjunto de puntas de electrodos.
DE502006003937D1 (de) Flächige beleuchtungseinrichtung
WO2008153737A3 (en) Power system with multiple generator units
ITMI20111846A1 (it) Procedimento per produrre un circuito elettrico e circuito elettrico
WO2009051834A3 (en) System, method and apparatus for creating an electric glow discharge
TW200514331A (en) Modifying surfaces of devices to integrate them into wireless charging systems
DE602005004265D1 (de) Kabelkappsystem
WO2010037934A3 (fr) Procède d'organisation d'un réseau électrique comportant plusieurs générateurs, répartiteur et installations.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition