DE60319705D1 - Integrierte schaltung und verfahren zur herstellung - Google Patents
Integrierte schaltung und verfahren zur herstellungInfo
- Publication number
- DE60319705D1 DE60319705D1 DE60319705T DE60319705T DE60319705D1 DE 60319705 D1 DE60319705 D1 DE 60319705D1 DE 60319705 T DE60319705 T DE 60319705T DE 60319705 T DE60319705 T DE 60319705T DE 60319705 D1 DE60319705 D1 DE 60319705D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- manufacturing
- ports
- integrated
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
- H01L2223/6633—Transition between different waveguide types
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1903—Structure including wave guides
- H01L2924/19038—Structure including wave guides being a hybrid line type
- H01L2924/19039—Structure including wave guides being a hybrid line type impedance transition between different types of wave guides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE60319705T DE60319705T2 (de) | 2002-06-06 | 2003-05-27 | Integrierte schaltung und verfahren zur herstellung |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10225042 | 2002-06-06 | ||
DE10225042A DE10225042A1 (de) | 2002-06-06 | 2002-06-06 | Integrierter Schaltkreis und Verfahren zur Herstellung desselben |
DE60319705T DE60319705T2 (de) | 2002-06-06 | 2003-05-27 | Integrierte schaltung und verfahren zur herstellung |
PCT/IB2003/002712 WO2003105186A2 (en) | 2002-06-06 | 2003-05-27 | Integrated circuit and method for manufacturing same |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60319705D1 true DE60319705D1 (de) | 2008-04-24 |
DE60319705T2 DE60319705T2 (de) | 2009-03-12 |
Family
ID=29718865
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10225042A Ceased DE10225042A1 (de) | 2002-06-06 | 2002-06-06 | Integrierter Schaltkreis und Verfahren zur Herstellung desselben |
DE60319705T Expired - Fee Related DE60319705T2 (de) | 2002-06-06 | 2003-05-27 | Integrierte schaltung und verfahren zur herstellung |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10225042A Ceased DE10225042A1 (de) | 2002-06-06 | 2002-06-06 | Integrierter Schaltkreis und Verfahren zur Herstellung desselben |
Country Status (7)
Country | Link |
---|---|
US (1) | US20050231299A1 (de) |
EP (1) | EP1523784B1 (de) |
CN (1) | CN1672288A (de) |
AT (1) | ATE389245T1 (de) |
AU (1) | AU2003238631A1 (de) |
DE (2) | DE10225042A1 (de) |
WO (1) | WO2003105186A2 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10350033A1 (de) | 2003-10-27 | 2005-05-25 | Robert Bosch Gmbh | Bauelement mit Koplanarleitung |
DE102018200647A1 (de) | 2018-01-16 | 2019-07-18 | Vega Grieshaber Kg | Radar-transceiver-chip |
CN108871251B (zh) * | 2018-07-25 | 2020-07-07 | 上海高科工程咨询监理有限公司 | 装配有防撞除尘装置的坐标测量装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69012501T2 (de) * | 1989-02-02 | 1995-03-09 | Fujitsu Ltd | Filmförmiger abschlusswiderstand für microstripleitung. |
JPH0821807B2 (ja) * | 1993-04-07 | 1996-03-04 | 日本電気株式会社 | マイクロ波回路モジュールの製造装置 |
US6498582B1 (en) * | 1998-06-19 | 2002-12-24 | Raytheon Company | Radio frequency receiving circuit having a passive monopulse comparator |
JP3287309B2 (ja) * | 1998-07-06 | 2002-06-04 | 株式会社村田製作所 | 方向性結合器、アンテナ装置及び送受信装置 |
JP3350457B2 (ja) * | 1998-10-19 | 2002-11-25 | 株式会社東芝 | マイクロ波可変減衰回路 |
JP2001185912A (ja) * | 1999-10-13 | 2001-07-06 | Murata Mfg Co Ltd | 非可逆回路素子および通信装置 |
US6674339B2 (en) * | 2001-09-07 | 2004-01-06 | The Boeing Company | Ultra wideband frequency dependent attenuator with constant group delay |
-
2002
- 2002-06-06 DE DE10225042A patent/DE10225042A1/de not_active Ceased
-
2003
- 2003-05-27 US US10/517,301 patent/US20050231299A1/en not_active Abandoned
- 2003-05-27 CN CNA038184869A patent/CN1672288A/zh active Pending
- 2003-05-27 DE DE60319705T patent/DE60319705T2/de not_active Expired - Fee Related
- 2003-05-27 EP EP03732971A patent/EP1523784B1/de not_active Expired - Lifetime
- 2003-05-27 AU AU2003238631A patent/AU2003238631A1/en not_active Abandoned
- 2003-05-27 AT AT03732971T patent/ATE389245T1/de not_active IP Right Cessation
- 2003-05-27 WO PCT/IB2003/002712 patent/WO2003105186A2/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US20050231299A1 (en) | 2005-10-20 |
ATE389245T1 (de) | 2008-03-15 |
CN1672288A (zh) | 2005-09-21 |
EP1523784B1 (de) | 2008-03-12 |
AU2003238631A8 (en) | 2003-12-22 |
WO2003105186A2 (en) | 2003-12-18 |
WO2003105186A3 (en) | 2004-05-21 |
EP1523784A2 (de) | 2005-04-20 |
AU2003238631A1 (en) | 2003-12-22 |
DE60319705T2 (de) | 2009-03-12 |
DE10225042A1 (de) | 2004-01-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ATE324069T1 (de) | Verdrahtungsverfahren und gerät für eine ultraschallsonde | |
TW200519697A (en) | Technique for evaluating a fabrication of a semiconductor component and wafer | |
WO2004084277A3 (en) | Retiming circuits using a cut-based approach | |
EP1341214A4 (de) | Methode zur identifizierung eines halbleitenden integrierten schaltkreisbauelementes, dessen herstellungsverfahren sowie halbleitendes schaltkreisbauelement und halbleiterchip | |
WO2008042447A3 (en) | Method and system for the modular design and layout of integrated circuits | |
DE60127602D1 (de) | Verfahren zur Herstellung von Halbleiterchips | |
DE50101037D1 (de) | Verfahren zur herstellung eines trägerbandes mit einer vielzahl von elektrischen einheiten, jeweils aufweisend einen chip und kontaktelemente | |
DE602005014980D1 (de) | Verfahren und vorrichtung für widerstand gegen har | |
TW200630835A (en) | System and method for verifying/optimizing design of semiconductor integrated circuits | |
ATE503251T1 (de) | Verfahren zur bereitstellung optimaler einsatzortprogrammierung von elektronischen schmelzverbindungen | |
TW200717763A (en) | Tape carrier for TAB and method of manufacturing the same | |
EP4186101A4 (de) | Integrierte halbleiterschaltung und verfahren zu ihrer herstellung | |
DE60306893D1 (de) | Verfahren zur Herstellung einer elektrischen Speichereinrichtung mit Auswahltransistoren für Speicherelemente sowie entsprechend hergestellte Speichereinrichtung | |
ATE389245T1 (de) | Integrierte schaltung und verfahren zur herstellung | |
DE502004009020D1 (de) | Integrierte schaltung mit einem organischen halbleiter und verfahren zur herstellung einer integrierten schaltung | |
EP1294017A3 (de) | Chipherstellungsmethode bei der Prüfkontakte vom IC getrennt werden indem die Schaltungschips aus der Scheibe geschnitten werden | |
ATE506645T1 (de) | Verfahren und vorrichtung zur bereitstellung eines benutzerprioritätsmodus | |
DE502004000545D1 (de) | Elektronisches bauteil mit halbleiterchip und verfahren zur herstellung desselben | |
DE502008001773D1 (de) | Verfahren zur herstellung einer leiterplatte mit einer kavität für die integration von bauteilen | |
WO2009035868A3 (en) | Intelligent inspection based on test chip probe failure maps | |
ATE408153T1 (de) | Integrierte schaltung und verfahren zum prüfen einer integrierten schaltung mit mehreren abgriffen | |
EP1388890A4 (de) | Verfahren zur herstellung einer elektronischen komponente | |
ATE485597T1 (de) | Integrierte schaltungen auf einem wafer und verfahren zur herstellung integrierter schaltungen | |
TW200644208A (en) | Integrated circuit having a programmable conductive path on each conductive layer and related method of modifying a version number assigned to the integrated circuit | |
DE60203322D1 (de) | Verfahren zur herstellung eines halbleiterbauelements |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |