DE60237699D1 - Takt- und synchronisations-schaltung - Google Patents

Takt- und synchronisations-schaltung

Info

Publication number
DE60237699D1
DE60237699D1 DE60237699T DE60237699T DE60237699D1 DE 60237699 D1 DE60237699 D1 DE 60237699D1 DE 60237699 T DE60237699 T DE 60237699T DE 60237699 T DE60237699 T DE 60237699T DE 60237699 D1 DE60237699 D1 DE 60237699D1
Authority
DE
Germany
Prior art keywords
clock
synchronization switching
synchronization
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60237699T
Other languages
English (en)
Inventor
Raj Kumar Jain
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60237699D1 publication Critical patent/DE60237699D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels
    • H03K2005/00247—Layout of the delay element using circuits having two logic levels using counters
DE60237699T 2001-11-06 2002-11-06 Takt- und synchronisations-schaltung Expired - Lifetime DE60237699D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US33322001P 2001-11-06 2001-11-06
US10/116,601 US6621304B2 (en) 2001-11-06 2002-04-04 Clocking and synchronization circuitry
PCT/EP2002/012390 WO2003040900A2 (en) 2001-11-06 2002-11-06 Clocking and synchronization circuitry

Publications (1)

Publication Number Publication Date
DE60237699D1 true DE60237699D1 (de) 2010-10-28

Family

ID=26814402

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60237699T Expired - Lifetime DE60237699D1 (de) 2001-11-06 2002-11-06 Takt- und synchronisations-schaltung

Country Status (4)

Country Link
US (1) US6621304B2 (de)
EP (1) EP1442353B1 (de)
DE (1) DE60237699D1 (de)
WO (1) WO2003040900A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2002321951A1 (en) * 2002-08-30 2004-03-19 Telefonaktiebolaget Lm Ericsson (Publ) Method and arrangement for reducing phase jumps when switching between synchronisation sources
JP4511288B2 (ja) * 2004-09-01 2010-07-28 三洋電機株式会社 チャージポンプ回路
US7941604B2 (en) * 2006-02-01 2011-05-10 Infineon Technologies Ag Distributed memory usage for a system having multiple integrated circuits each including processors
ATE554368T1 (de) * 2008-07-23 2012-05-15 Sick Stegmann Gmbh Verfahren zur digitalen, bidirektionalen datenübertragung
WO2020131681A1 (en) * 2018-12-18 2020-06-25 Knowles Electronics, Llc Audio level estimator assisted false wake abatement systems and methods

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3689439T2 (de) * 1985-10-07 1994-07-14 Yamaha Corp Synchronisationsschaltung für eine Videoplattenwiedergabevorrichtung.
JPH03175833A (ja) * 1989-12-05 1991-07-30 Matsushita Electric Ind Co Ltd Ｍｕｓｅ信号の同期再生装置
EP0596651A1 (de) * 1992-11-02 1994-05-11 National Semiconductor Corporation Datennetz mit isochroner Übertragungsfähigkeit
US5677935A (en) * 1995-01-11 1997-10-14 Matsuhita Electric Industrial Co., Ltd. Sync detecting method and sync detecting circuit
GB2311195B (en) 1996-03-13 2000-03-15 Madge Networks Ltd Methods and apparatus for synchronizing a clock
US6278718B1 (en) * 1996-08-29 2001-08-21 Excel, Inc. Distributed network synchronization system
US5914991A (en) 1997-06-30 1999-06-22 Siemens Medical Systems, Inc. Syncronizing a data acquisition device with a host
US6064235A (en) * 1998-03-18 2000-05-16 International Business Machines Corporation Shared path phase detector
JP2001016586A (ja) * 1999-07-01 2001-01-19 Matsushita Electric Ind Co Ltd 画像復号化装置
US6285172B1 (en) 2000-11-13 2001-09-04 Texas Instruments Incorporated Digital phase-locked loop circuit with reduced phase jitter frequency

Also Published As

Publication number Publication date
WO2003040900A3 (en) 2004-01-29
WO2003040900A2 (en) 2003-05-15
EP1442353B1 (de) 2010-09-15
US20030085742A1 (en) 2003-05-08
US6621304B2 (en) 2003-09-16
EP1442353A2 (de) 2004-08-04

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