DE60140791D1 - Taktrückgewinnungsschaltung und Empfangsschaltung - Google Patents

Taktrückgewinnungsschaltung und Empfangsschaltung

Info

Publication number
DE60140791D1
DE60140791D1 DE60140791T DE60140791T DE60140791D1 DE 60140791 D1 DE60140791 D1 DE 60140791D1 DE 60140791 T DE60140791 T DE 60140791T DE 60140791 T DE60140791 T DE 60140791T DE 60140791 D1 DE60140791 D1 DE 60140791D1
Authority
DE
Germany
Prior art keywords
circuit
clock recovery
receiving
receiving circuit
recovery circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60140791T
Other languages
English (en)
Inventor
Takuya Saze
Hirotaka Tamura
Takaya Chiba
Kohtaroh Gotoh
Hideki Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2001096805A external-priority patent/JP4229599B2/ja
Priority claimed from JP2001118548A external-priority patent/JP4233236B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60140791D1 publication Critical patent/DE60140791D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE60140791T 2001-03-29 2001-10-19 Taktrückgewinnungsschaltung und Empfangsschaltung Expired - Lifetime DE60140791D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001096805A JP4229599B2 (ja) 2001-03-29 2001-03-29 クロック復元回路および受信回路
JP2001118548A JP4233236B2 (ja) 2001-04-17 2001-04-17 クロック復元回路および受信回路

Publications (1)

Publication Number Publication Date
DE60140791D1 true DE60140791D1 (de) 2010-01-28

Family

ID=26612596

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60140791T Expired - Lifetime DE60140791D1 (de) 2001-03-29 2001-10-19 Taktrückgewinnungsschaltung und Empfangsschaltung

Country Status (3)

Country Link
US (1) US7116744B2 (de)
EP (1) EP1246388B1 (de)
DE (1) DE60140791D1 (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030093354A1 (en) * 2001-05-16 2003-05-15 Marshall David J. Method for hedging one or more liabilities associated with a deferred compensation plan and for recordkeeping information of such a hedge
EP1446910B1 (de) 2001-10-22 2010-08-11 Rambus Inc. Phaseneinstellvorrichtung und verfahren für ein speicherbaustein-signalisierungssystem
US7515656B2 (en) * 2002-04-15 2009-04-07 Fujitsu Limited Clock recovery circuit and data receiving circuit
JP4121863B2 (ja) 2003-01-29 2008-07-23 富士通株式会社 タイミング信号発生回路および受信回路
KR100574938B1 (ko) * 2003-02-20 2006-04-28 삼성전자주식회사 고속 직렬 링크에서 데이터 복원시 에러 발생을감소시키는 데이터 복원장치 및 그 복원방법
US7260001B2 (en) * 2003-03-20 2007-08-21 Arm Limited Memory system having fast and slow data reading mechanisms
US8185812B2 (en) 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
DE602004001869T2 (de) * 2003-03-20 2007-05-03 Arm Ltd., Cherry Hinton Fehlererkennung und fehlerbehebung für systematische und zufällige fehler innerhalb einer verarbeitungsstufe einer integrierten schaltung
US7512188B1 (en) * 2003-04-10 2009-03-31 Xilinx, Inc. Phase shift keying signaling for integrated circuits
DE102004013929B3 (de) * 2004-03-22 2005-08-11 Infineon Technologies Ag Verfahren zum Steuern des Einlesens eines Datensignals sowie eine Eingangsschaltung für eine elektronische Schaltung
US7506193B1 (en) * 2005-03-04 2009-03-17 Unisys Corporation Systems and methods for overcoming part to part skew in a substrate-mounted circuit
JP4749168B2 (ja) * 2006-02-01 2011-08-17 ルネサスエレクトロニクス株式会社 クロックアンドデータリカバリ回路
CN101606318B (zh) * 2007-02-09 2012-10-31 Nxp股份有限公司 集成电路，数字电子装置以及改变数字电子装置中时钟延迟的方法
JP4930593B2 (ja) * 2007-07-24 2012-05-16 日本電気株式会社 データ転送装置およびデータ転送方法
US8171386B2 (en) * 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8161367B2 (en) * 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
JP4924630B2 (ja) * 2009-02-06 2012-04-25 富士通株式会社 クロック生成回路
JP5560867B2 (ja) 2010-04-12 2014-07-30 富士通株式会社 データ受信回路
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
US8959380B2 (en) 2012-05-09 2015-02-17 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Dynamically optimizing bus frequency of an inter-integrated circuit (‘I2C’) bus
US9385858B2 (en) * 2013-02-20 2016-07-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Timing phase estimation for clock and data recovery
KR102092253B1 (ko) * 2013-08-09 2020-03-24 에스케이하이닉스 주식회사 데이터 복원 회로 및 그의 동작 방법
US9864398B2 (en) * 2015-12-30 2018-01-09 Texas Instruments Incorporated Embedded clock in a communication system
US10581417B2 (en) * 2017-09-29 2020-03-03 International Business Machines Corporation Skew sensor with enhanced reliability
US10270456B1 (en) * 2018-01-02 2019-04-23 Realtek Semiconductor Corp. Apparatus and method for frequency tripling
KR102455370B1 (ko) * 2018-04-17 2022-10-18 에스케이하이닉스 주식회사 데이터 아이를 개선하는 전송 회로, 이를 이용하는 반도체 장치 및 반도체 시스템
US11309876B2 (en) * 2019-11-18 2022-04-19 Macom Technology Solutions Holdings, Inc. Digitally programmable analog duty-cycle correction circuit
JP2022049496A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体集積回路及び受信装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4535459A (en) 1983-05-26 1985-08-13 Rockwell International Corporation Signal detection apparatus
US4821297A (en) 1987-11-19 1989-04-11 American Telephone And Telegraph Company, At&T Bell Laboratories Digital phase locked loop clock recovery scheme
KR0132811B1 (ko) * 1994-12-31 1998-04-21 김광호 디지탈 데이터 복구장치
EP0758171A3 (de) 1995-08-09 1997-11-26 Symbios Logic Inc. Datenabtastung und -rückgewinnung
US5926053A (en) * 1995-12-15 1999-07-20 National Semiconductor Corporation Selectable clock generation mode
US6122336A (en) * 1997-09-11 2000-09-19 Lsi Logic Corporation Digital clock recovery circuit with phase interpolation
US5948083A (en) 1997-09-30 1999-09-07 S3 Incorporated System and method for self-adjusting data strobe
EP1061691A3 (de) 1999-06-15 2005-05-25 Matsushita Electric Industrial Co., Ltd. Digitale PLL-Schaltung für Burstbetrieb und optische Empfangsschaltung, die dieselbe verwendet
US6262611B1 (en) 1999-06-24 2001-07-17 Nec Corporation High-speed data receiving circuit and method
WO2001006696A1 (en) 1999-07-16 2001-01-25 Conexant Systems, Inc. Apparatus and method for servo-controlled self-centering phase detector

Also Published As

Publication number Publication date
US20020172304A1 (en) 2002-11-21
EP1246388A2 (de) 2002-10-02
US7116744B2 (en) 2006-10-03
EP1246388B1 (de) 2009-12-16
EP1246388A3 (de) 2006-06-07

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Legal Events

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8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE