DE60233352D1 - Modulus-zwei-vorskaliererschaltung - Google Patents
Modulus-zwei-vorskaliererschaltungInfo
- Publication number
- DE60233352D1 DE60233352D1 DE60233352T DE60233352T DE60233352D1 DE 60233352 D1 DE60233352 D1 DE 60233352D1 DE 60233352 T DE60233352 T DE 60233352T DE 60233352 T DE60233352 T DE 60233352T DE 60233352 D1 DE60233352 D1 DE 60233352D1
- Authority
- DE
- Germany
- Prior art keywords
- vorskaliererschaltung
- modulus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001386873A JP3857916B2 (ja) | 2001-12-20 | 2001-12-20 | 2モジュラスプリスケーラ回路 |
PCT/JP2002/013190 WO2003058817A1 (fr) | 2001-12-20 | 2002-12-17 | Circuit generateur d'echelles a deux modules |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60233352D1 true DE60233352D1 (de) | 2009-09-24 |
Family
ID=19188003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60233352T Expired - Fee Related DE60233352D1 (de) | 2001-12-20 | 2002-12-17 | Modulus-zwei-vorskaliererschaltung |
Country Status (5)
Country | Link |
---|---|
US (1) | US20050116258A1 (de) |
EP (1) | EP1469604B1 (de) |
JP (1) | JP3857916B2 (de) |
DE (1) | DE60233352D1 (de) |
WO (1) | WO2003058817A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7248665B2 (en) * | 2005-04-27 | 2007-07-24 | Winbond Electronics Corp. | Prescaler |
DE102005042310A1 (de) * | 2005-09-06 | 2007-03-15 | Infineon Technologies Ag | CMOS-Schaltkreis-Anordnung |
US7656234B2 (en) | 2007-10-19 | 2010-02-02 | Advantest Corporation | Circuit and oscillating apparatus |
US7859344B2 (en) * | 2008-04-29 | 2010-12-28 | Renesas Electronics Corporation | PLL circuit with improved phase difference detection |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4695743A (en) * | 1985-10-23 | 1987-09-22 | Hughes Aircraft Company | Multiple input dissymmetric latch |
US4933347A (en) * | 1988-10-25 | 1990-06-12 | University Of North Carolina At Chapel Hill | Diamidines and bis(imidazolines) for the treatment of and prophylaxis against pneumocystis carinii pneumonia |
EP0683566A1 (de) * | 1994-05-17 | 1995-11-22 | Siemens Aktiengesellschaft | Schaltungsanordnung zum Teilen eines Taktsignals |
JPH08204541A (ja) * | 1995-01-30 | 1996-08-09 | Nec Corp | 半導体論理回路 |
US5818293A (en) * | 1997-02-26 | 1998-10-06 | Advanced Micro Devices, Inc. | High speed analog flip-flop with embedded logic and phase-locked-loop circuit employing the same |
US20020089353A1 (en) * | 1998-07-13 | 2002-07-11 | Abdellatif Bellaouar | Current mode logic gates for low-voltage high-speed applications |
US6157693A (en) * | 1998-09-30 | 2000-12-05 | Conexant Systems, Inc. | Low voltage dual-modulus prescaler circuit using merged pseudo-differential logic |
JP2001186012A (ja) * | 1999-12-27 | 2001-07-06 | Toshiba Corp | 分周回路 |
US6580293B1 (en) * | 2001-12-14 | 2003-06-17 | International Business Machines Corporation | Body-contacted and double gate-contacted differential logic circuit and method of operation |
-
2001
- 2001-12-20 JP JP2001386873A patent/JP3857916B2/ja not_active Expired - Lifetime
-
2002
- 2002-12-17 DE DE60233352T patent/DE60233352D1/de not_active Expired - Fee Related
- 2002-12-17 WO PCT/JP2002/013190 patent/WO2003058817A1/ja active Application Filing
- 2002-12-17 US US10/499,640 patent/US20050116258A1/en not_active Abandoned
- 2002-12-17 EP EP02786127A patent/EP1469604B1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3857916B2 (ja) | 2006-12-13 |
EP1469604A4 (de) | 2005-02-02 |
US20050116258A1 (en) | 2005-06-02 |
JP2003188716A (ja) | 2003-07-04 |
EP1469604B1 (de) | 2009-08-12 |
EP1469604A1 (de) | 2004-10-20 |
WO2003058817A1 (fr) | 2003-07-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |