DE60226986D1 - Mram bitleitungwortleitungsarchitektur - Google Patents

Mram bitleitungwortleitungsarchitektur

Info

Publication number
DE60226986D1
DE60226986D1 DE60226986T DE60226986T DE60226986D1 DE 60226986 D1 DE60226986 D1 DE 60226986D1 DE 60226986 T DE60226986 T DE 60226986T DE 60226986 T DE60226986 T DE 60226986T DE 60226986 D1 DE60226986 D1 DE 60226986D1
Authority
DE
Germany
Prior art keywords
bitleitungwortleitungsarchitektur
mram
mram bitleitungwortleitungsarchitektur
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60226986T
Other languages
English (en)
Inventor
Hans-Heinrich Viehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Qimonda AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qimonda AG filed Critical Qimonda AG
Application granted granted Critical
Publication of DE60226986D1 publication Critical patent/DE60226986D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
DE60226986T 2001-01-24 2002-01-24 Mram bitleitungwortleitungsarchitektur Expired - Lifetime DE60226986D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US26398401P 2001-01-24 2001-01-24
US09/965,086 US6584006B2 (en) 2001-01-24 2001-09-27 MRAM bit line word line architecture
PCT/US2002/001925 WO2002059899A2 (en) 2001-01-24 2002-01-24 Mram bit line word line architecture

Publications (1)

Publication Number Publication Date
DE60226986D1 true DE60226986D1 (de) 2008-07-17

Family

ID=26950183

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60226986T Expired - Lifetime DE60226986D1 (de) 2001-01-24 2002-01-24 Mram bitleitungwortleitungsarchitektur

Country Status (8)

Country Link
US (1) US6584006B2 (de)
EP (1) EP1435098B1 (de)
JP (1) JP3996061B2 (de)
KR (1) KR100565109B1 (de)
CN (1) CN100338683C (de)
DE (1) DE60226986D1 (de)
TW (1) TW546650B (de)
WO (1) WO2002059899A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7005350B2 (en) * 2002-12-31 2006-02-28 Matrix Semiconductor, Inc. Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US7505321B2 (en) * 2002-12-31 2009-03-17 Sandisk 3D Llc Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US7233522B2 (en) 2002-12-31 2007-06-19 Sandisk 3D Llc NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
US6822903B2 (en) * 2003-03-31 2004-11-23 Matrix Semiconductor, Inc. Apparatus and method for disturb-free programming of passive element memory cells
US7233024B2 (en) 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
US6879505B2 (en) * 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US7177183B2 (en) 2003-09-30 2007-02-13 Sandisk 3D Llc Multiple twin cell non-volatile memory array and logic block structure and method therefor
US6972989B2 (en) 2003-10-10 2005-12-06 Infincon Technologies Ag Reference current distribution in MRAM devices
US6873535B1 (en) * 2004-02-04 2005-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple width and/or thickness write line in MRAM
DE602005022398D1 (de) * 2004-11-30 2010-09-02 Toshiba Kk Anordnung der Schreiblinien in einer MRAM-Vorrichtung
JP4388008B2 (ja) * 2004-11-30 2009-12-24 株式会社東芝 半導体記憶装置
US7272052B2 (en) * 2005-03-31 2007-09-18 Sandisk 3D Llc Decoding circuit for non-binary groups of memory line drivers
US7054219B1 (en) 2005-03-31 2006-05-30 Matrix Semiconductor, Inc. Transistor layout configuration for tight-pitched memory array lines
US7142471B2 (en) * 2005-03-31 2006-11-28 Sandisk 3D Llc Method and apparatus for incorporating block redundancy in a memory array
US7359279B2 (en) * 2005-03-31 2008-04-15 Sandisk 3D Llc Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
US7480172B2 (en) 2006-01-25 2009-01-20 Magic Technologies, Inc. Programming scheme for segmented word line MRAM array
JP5045671B2 (ja) * 2006-06-08 2012-10-10 日本電気株式会社 Ｍｒａｍにおける電流終端回路
KR100758299B1 (ko) * 2006-07-25 2007-09-12 삼성전자주식회사 플래쉬 메모리 장치 및 그것의 쓰기 방법
JP2020155181A (ja) * 2019-03-20 2020-09-24 キオクシア株式会社 半導体メモリ装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3101802A1 (de) 1981-01-21 1982-08-19 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierter halbleiterspeicher
US5024993A (en) * 1990-05-02 1991-06-18 Microelectronics & Computer Technology Corporation Superconducting-semiconducting circuits, devices and systems
JPH06318683A (ja) * 1993-05-01 1994-11-15 Toshiba Corp 半導体記憶装置及びその製造方法
JP3560266B2 (ja) 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
DE19853447A1 (de) * 1998-11-19 2000-05-25 Siemens Ag Magnetischer Speicher
US6111783A (en) 1999-06-16 2000-08-29 Hewlett-Packard Company MRAM device including write circuit for supplying word and bit line current having unequal magnitudes

Also Published As

Publication number Publication date
EP1435098A2 (de) 2004-07-07
EP1435098B1 (de) 2008-06-04
JP2004518288A (ja) 2004-06-17
US6584006B2 (en) 2003-06-24
TW546650B (en) 2003-08-11
CN100338683C (zh) 2007-09-19
US20020097597A1 (en) 2002-07-25
KR20040012715A (ko) 2004-02-11
WO2002059899A2 (en) 2002-08-01
KR100565109B1 (ko) 2006-03-30
WO2002059899A3 (en) 2003-02-13
CN1488145A (zh) 2004-04-07
JP3996061B2 (ja) 2007-10-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition