DE60220863D1 - Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten - Google Patents

Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten

Info

Publication number
DE60220863D1
DE60220863D1 DE60220863T DE60220863T DE60220863D1 DE 60220863 D1 DE60220863 D1 DE 60220863D1 DE 60220863 T DE60220863 T DE 60220863T DE 60220863 T DE60220863 T DE 60220863T DE 60220863 D1 DE60220863 D1 DE 60220863D1
Authority
DE
Germany
Prior art keywords
coordinating
differently located
storage
operations
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60220863T
Other languages
English (en)
Other versions
DE60220863T2 (de
Inventor
Frederick A Ware
Ely K Tsern
Richard E Perego
Craig E Hampel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26731741&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60220863(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Priority claimed from US09/841,911 external-priority patent/US6675272B2/en
Application filed by Rambus Inc filed Critical Rambus Inc
Application granted granted Critical
Publication of DE60220863D1 publication Critical patent/DE60220863D1/de
Publication of DE60220863T2 publication Critical patent/DE60220863T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
DE2002620863 2001-04-24 2002-04-23 Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten Expired - Lifetime DE60220863T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/841,911 US6675272B2 (en) 2001-04-24 2001-04-24 Method and apparatus for coordinating memory operations among diversely-located memory components
US841911 2001-04-24
US10/053,340 US7484064B2 (en) 2001-04-24 2001-10-22 Method and apparatus for signaling between devices of a memory system
US53340 2001-10-22

Publications (2)

Publication Number Publication Date
DE60220863D1 true DE60220863D1 (de) 2007-08-09
DE60220863T2 DE60220863T2 (de) 2008-03-13

Family

ID=26731741

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2002620863 Expired - Lifetime DE60220863T2 (de) 2001-04-24 2002-04-23 Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten

Country Status (3)

Country Link
EP (2) EP1291778B1 (de)
JP (1) JP4535664B2 (de)
DE (1) DE60220863T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
JP4159415B2 (ja) 2002-08-23 2008-10-01 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
US7188208B2 (en) * 2004-09-07 2007-03-06 Intel Corporation Side-by-side inverted memory address and command buses
US7571296B2 (en) * 2004-11-11 2009-08-04 Nvidia Corporation Memory controller-adaptive 1T/2T timing control
US7996590B2 (en) * 2004-12-30 2011-08-09 Samsung Electronics Co., Ltd. Semiconductor memory module and semiconductor memory system having termination resistor units
DE102005013238B4 (de) 2005-03-22 2015-07-16 Infineon Technologies Ag Verfahren und Einrichtung zum Übertragen von Justierinformation für Datenschnittstellen-Treiber eines RAM-Bausteins
US8370581B2 (en) * 2005-06-30 2013-02-05 Intel Corporation System and method for dynamic data prefetching
US9384128B2 (en) 2014-04-18 2016-07-05 SanDisk Technologies, Inc. Multi-level redundancy code for non-volatile memory controller
JP7176305B2 (ja) * 2018-09-03 2022-11-22 株式会社オートネットワーク技術研究所 中継装置、中継方法及びコンピュータプログラム
FR3100629B1 (fr) * 2019-09-10 2023-04-07 St Microelectronics Grenoble 2 Communication par bus CAN
FR3100628B1 (fr) * 2019-09-10 2023-04-14 St Microelectronics Grenoble 2 Communication par bus CAN

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3543336B2 (ja) * 1993-07-20 2004-07-14 株式会社ルネサステクノロジ 半導体装置および半導体装置の配線方式
JP3328638B2 (ja) * 1994-01-21 2002-09-30 株式会社日立製作所 メモリ装置
US6226723B1 (en) * 1996-09-20 2001-05-01 Advanced Memory International, Inc. Bifurcated data and command/address communication bus architecture for random access memories employing synchronous communication protocols
EP0831402A1 (de) * 1996-09-23 1998-03-25 Hewlett-Packard Company Dynamisches Konfigurieren des Zeitverhaltens zur Anpassung an Speicherbuslastbedingungen
US5892981A (en) * 1996-10-10 1999-04-06 Hewlett-Packard Company Memory system and device
KR19980064365A (ko) * 1996-12-19 1998-10-07 윌리엄비.켐플러 메모리 모듈로의 어드레스 및 데이타 분산용 장치 및 방법
DE69731066T2 (de) * 1997-01-23 2005-10-06 Hewlett-Packard Development Co., L.P., Houston Speichersteuerungsvorrichtung mit programmierbarer Impulsverzögerung
JP2935694B2 (ja) * 1997-04-25 1999-08-16 松下電器産業株式会社 半導体集積回路およびシステム、並びにクロック信号とデータ信号との間のスキューを低減する方法
JPH1185345A (ja) * 1997-09-02 1999-03-30 Toshiba Corp 入出力インターフェース回路及び半導体システム
KR100278653B1 (ko) * 1998-01-23 2001-02-01 윤종용 이중 데이터율 모드 반도체 메모리 장치
AU3021799A (en) * 1998-04-01 1999-10-18 Mosaid Technologies Incorporated Semiconductor memory asynchronous pipeline
KR100305647B1 (ko) * 1998-05-27 2002-03-08 박종섭 동기식메모리장치
KR100287542B1 (ko) * 1998-11-26 2001-04-16 윤종용 웨이브 파이프라인 스킴을 구비한 동기형 반도체 메모리 장치및 그것의 데이터 패스 제어 방법
JP3803204B2 (ja) * 1998-12-08 2006-08-02 寛治 大塚 電子装置
US6654897B1 (en) * 1999-03-05 2003-11-25 International Business Machines Corporation Dynamic wave-pipelined interface apparatus and methods therefor
US6137734A (en) * 1999-03-30 2000-10-24 Lsi Logic Corporation Computer memory interface having a memory controller that automatically adjusts the timing of memory interface signals
US6191997B1 (en) * 2000-03-10 2001-02-20 Mosel Vitelic Inc. Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.
US6675272B2 (en) * 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components

Also Published As

Publication number Publication date
EP1291778B1 (de) 2007-06-27
EP1253521A3 (de) 2006-12-13
DE60220863T2 (de) 2008-03-13
EP1291778A2 (de) 2003-03-12
EP1253521A2 (de) 2002-10-30
EP1291778A3 (de) 2005-08-17
EP1253521B1 (de) 2011-01-26
JP4535664B2 (ja) 2010-09-01
JP2002342154A (ja) 2002-11-29

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Legal Events

Date Code Title Description
8363 Opposition against the patent