DE60204994T2 - Reduzieren von Szintillationseffekten bei optischer Freiraumübertragung - Google Patents
Reduzieren von Szintillationseffekten bei optischer Freiraumübertragung Download PDFInfo
- Publication number
- DE60204994T2 DE60204994T2 DE60204994T DE60204994T DE60204994T2 DE 60204994 T2 DE60204994 T2 DE 60204994T2 DE 60204994 T DE60204994 T DE 60204994T DE 60204994 T DE60204994 T DE 60204994T DE 60204994 T2 DE60204994 T2 DE 60204994T2
- Authority
- DE
- Germany
- Prior art keywords
- sdram
- read
- write
- page
- sub
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/11—Arrangements specific to free-space transmission, i.e. transmission through air or vacuum
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Algebra (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Detection And Correction Of Errors (AREA)
- Memory System (AREA)
- Road Signs Or Road Markings (AREA)
- Optical Communication System (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US839486 | 2001-04-23 | ||
| US09/839,486 US6868519B2 (en) | 2001-04-23 | 2001-04-23 | Reducing scintillation effects for optical free-space transmission |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60204994D1 DE60204994D1 (de) | 2005-08-18 |
| DE60204994T2 true DE60204994T2 (de) | 2006-04-27 |
Family
ID=25279853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60204994T Expired - Lifetime DE60204994T2 (de) | 2001-04-23 | 2002-03-22 | Reduzieren von Szintillationseffekten bei optischer Freiraumübertragung |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6868519B2 (enExample) |
| EP (1) | EP1253729B1 (enExample) |
| JP (1) | JP4108359B2 (enExample) |
| AT (1) | ATE299627T1 (enExample) |
| DE (1) | DE60204994T2 (enExample) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1218314C (zh) * | 1999-12-17 | 2005-09-07 | 汤姆森特许公司 | 用同步动态随机存取存储器作为光记录或再现设备前端集成电路中纠错和轨道缓冲的存储器 |
| US7158517B2 (en) * | 2001-05-21 | 2007-01-02 | Intel Corporation | Method and apparatus for frame-based protocol processing |
| JP4077355B2 (ja) * | 2003-04-16 | 2008-04-16 | 三菱電機株式会社 | 通信装置および通信方法 |
| US7408913B2 (en) * | 2003-05-12 | 2008-08-05 | Lucent Technologies Inc. | Method of real time hybrid ARQ |
| US8644341B1 (en) * | 2003-09-26 | 2014-02-04 | Sigma Designs Israel S.D.I. Ltd | MAC structure with packet-quasi-static blocks and ARQ |
| KR100596435B1 (ko) | 2003-12-17 | 2006-07-05 | 주식회사 하이닉스반도체 | 어드레스 억세스타임을 줄일 수 있는 반도체 메모리 장치 |
| US7835264B2 (en) * | 2004-12-29 | 2010-11-16 | Mitsubishi Denki Kabushiki Kaisha | Interleaver, deinterleaver, communication device, and method for interleaving and deinterleaving |
| US20060176966A1 (en) * | 2005-02-07 | 2006-08-10 | Stewart Kenneth A | Variable cyclic prefix in mixed-mode wireless communication systems |
| US20060245384A1 (en) * | 2005-05-02 | 2006-11-02 | Talukdar Anup K | Method and apparatus for transmitting data |
| US7649788B2 (en) * | 2006-01-30 | 2010-01-19 | Unity Semiconductor Corporation | Buffering systems for accessing multiple layers of memory in integrated circuits |
| KR100764052B1 (ko) * | 2006-08-03 | 2007-10-08 | 삼성전자주식회사 | 유동적 어드레스 바운더리를 갖는 플래시 메모리 장치 및그것의 프로그램 방법 |
| US8400998B2 (en) | 2006-08-23 | 2013-03-19 | Motorola Mobility Llc | Downlink control channel signaling in wireless communication systems |
| US8392955B2 (en) * | 2007-09-04 | 2013-03-05 | Hayim Shaul | Apparatus and method for representing a sequence of content as projections for reconstructing the sequence at full or lower quality |
| US7941711B2 (en) * | 2007-12-04 | 2011-05-10 | Texas Instruments Incorporated | Determining bit error rate using single data burst |
| CN102801488B (zh) * | 2011-05-23 | 2015-12-16 | 中兴通讯股份有限公司 | 一种适用于WiMAX的交织或解交织的实现方法和装置 |
| FR2986889B1 (fr) * | 2012-02-09 | 2014-10-17 | Thales Sa | Systeme de paiement, terminal de paiement de ce systeme, et procede de paiement associe |
| GB2497154B (en) * | 2012-08-30 | 2013-10-16 | Imagination Tech Ltd | Tile based interleaving and de-interleaving for digital signal processing |
| JP6988092B2 (ja) * | 2017-01-16 | 2022-01-05 | 富士通株式会社 | 並列処理装置およびバーストエラー再現方法 |
| US10784986B2 (en) | 2017-02-28 | 2020-09-22 | Intel Corporation | Forward error correction mechanism for peripheral component interconnect-express (PCI-e) |
| US10289330B2 (en) * | 2017-03-30 | 2019-05-14 | Western Digital Technologies, Inc. | Allocating shared memory among multiple tasks in a multiprocessor environment |
| CN109495207B (zh) * | 2017-09-11 | 2021-08-10 | 上海诺基亚贝尔股份有限公司 | 用于在无线通信系统中交织数据的方法和设备 |
| US10771189B2 (en) | 2018-12-18 | 2020-09-08 | Intel Corporation | Forward error correction mechanism for data transmission across multi-lane links |
| US11637657B2 (en) | 2019-02-15 | 2023-04-25 | Intel Corporation | Low-latency forward error correction for high-speed serial links |
| US11249837B2 (en) | 2019-03-01 | 2022-02-15 | Intel Corporation | Flit-based parallel-forward error correction and parity |
| US11296994B2 (en) | 2019-05-13 | 2022-04-05 | Intel Corporation | Ordered sets for high-speed interconnects |
| US11740958B2 (en) | 2019-11-27 | 2023-08-29 | Intel Corporation | Multi-protocol support on common physical layer |
| US12189470B2 (en) | 2020-09-18 | 2025-01-07 | Intel Corporation | Forward error correction and cyclic redundancy check mechanisms for latency-critical coherency and memory interconnects |
| US20250112697A1 (en) * | 2023-09-28 | 2025-04-03 | Rosemount Aerospace Inc. | Aircraft to airport laser communication |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5063533A (en) | 1989-04-10 | 1991-11-05 | Motorola, Inc. | Reconfigurable deinterleaver/interleaver for block oriented data |
| US5907563A (en) * | 1996-03-07 | 1999-05-25 | Kokusai Denshin Denwa Co. Ltd. | Error control method and apparatus for wireless data communication |
| US5889791A (en) | 1996-08-13 | 1999-03-30 | Motorola, Inc. | System, device and method of FEC coding and interleaving for variable length burst transmission |
| US6044429A (en) * | 1997-07-10 | 2000-03-28 | Micron Technology, Inc. | Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths |
| US6075824A (en) | 1997-08-04 | 2000-06-13 | Motorola, Inc. | Method and apparatus for re-encoding decoded data |
| GB2334641A (en) * | 1998-02-11 | 1999-08-25 | Northern Telecom Ltd | Multiplexed transmission of optical signals |
| JP4110613B2 (ja) * | 1998-04-22 | 2008-07-02 | ソニー株式会社 | 送信装置、送信方法、提供媒体、並びに伝送システム |
| US6163871A (en) * | 1998-05-29 | 2000-12-19 | Adaptec, Inc. | RAM based error correction code encoder and syndrome generator with programmable interleaving degrees |
| DE19951677B4 (de) * | 1998-10-30 | 2006-04-13 | Fujitsu Ltd., Kawasaki | Halbleiterspeichervorrichtung |
| US6625763B1 (en) * | 2000-07-05 | 2003-09-23 | 3G.Com, Inc. | Block interleaver and de-interleaver with buffer to reduce power consumption |
-
2001
- 2001-04-23 US US09/839,486 patent/US6868519B2/en not_active Expired - Lifetime
-
2002
- 2002-03-22 AT AT02252093T patent/ATE299627T1/de not_active IP Right Cessation
- 2002-03-22 EP EP02252093A patent/EP1253729B1/en not_active Expired - Lifetime
- 2002-03-22 DE DE60204994T patent/DE60204994T2/de not_active Expired - Lifetime
- 2002-04-22 JP JP2002119003A patent/JP4108359B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP4108359B2 (ja) | 2008-06-25 |
| ATE299627T1 (de) | 2005-07-15 |
| JP2003051813A (ja) | 2003-02-21 |
| EP1253729A2 (en) | 2002-10-30 |
| EP1253729B1 (en) | 2005-07-13 |
| US6868519B2 (en) | 2005-03-15 |
| US20020157060A1 (en) | 2002-10-24 |
| EP1253729A3 (en) | 2004-07-28 |
| DE60204994D1 (de) | 2005-08-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |